JP2014149906A5 - - Google Patents

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Publication number
JP2014149906A5
JP2014149906A5 JP2014012282A JP2014012282A JP2014149906A5 JP 2014149906 A5 JP2014149906 A5 JP 2014149906A5 JP 2014012282 A JP2014012282 A JP 2014012282A JP 2014012282 A JP2014012282 A JP 2014012282A JP 2014149906 A5 JP2014149906 A5 JP 2014149906A5
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JP
Japan
Prior art keywords
voltage
readings
nominal
bit digital
digital pattern
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JP2014012282A
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English (en)
Japanese (ja)
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JP6556423B2 (ja
JP2014149906A (ja
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Priority claimed from US13/757,027 external-priority patent/US8879324B2/en
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Publication of JP2014149906A publication Critical patent/JP2014149906A/ja
Publication of JP2014149906A5 publication Critical patent/JP2014149906A5/ja
Application granted granted Critical
Publication of JP6556423B2 publication Critical patent/JP6556423B2/ja
Active legal-status Critical Current
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JP2014012282A 2013-02-01 2014-01-27 読み取り電圧適応のための補償ループ Active JP6556423B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/757,027 2013-02-01
US13/757,027 US8879324B2 (en) 2013-02-01 2013-02-01 Compensation loop for read voltage adaptation

Publications (3)

Publication Number Publication Date
JP2014149906A JP2014149906A (ja) 2014-08-21
JP2014149906A5 true JP2014149906A5 (enExample) 2017-03-02
JP6556423B2 JP6556423B2 (ja) 2019-08-07

Family

ID=49999755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014012282A Active JP6556423B2 (ja) 2013-02-01 2014-01-27 読み取り電圧適応のための補償ループ

Country Status (6)

Country Link
US (1) US8879324B2 (enExample)
EP (1) EP2763140A2 (enExample)
JP (1) JP6556423B2 (enExample)
KR (1) KR102180452B1 (enExample)
CN (1) CN103971723B (enExample)
TW (1) TWI613661B (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9286155B1 (en) * 2013-05-24 2016-03-15 Marvell International Ltd. Systems and methods for generating soft information in a flash device
US9633740B1 (en) * 2016-02-11 2017-04-25 Seagate Technology Llc Read retry operations where likelihood value assignments change sign at different read voltages for each read retry
US9818488B2 (en) * 2015-10-30 2017-11-14 Seagate Technology Llc Read threshold voltage adaptation using bit error rates based on decoded data
US9720754B2 (en) 2014-11-20 2017-08-01 Western Digital Technologies, Inc. Read level grouping for increased flash performance
US9576671B2 (en) 2014-11-20 2017-02-21 Western Digital Technologies, Inc. Calibrating optimal read levels
US9905302B2 (en) 2014-11-20 2018-02-27 Western Digital Technologies, Inc. Read level grouping algorithms for increased flash performance
KR102253592B1 (ko) * 2014-12-23 2021-05-18 삼성전자주식회사 초기 문턱 전압 분포 변화를 보상할 수 있는 데이터 저장 장치, 이의 작동 방법, 및 이를 포함하는 데이터 처리 시스템
GB2537484B (en) * 2015-03-20 2019-07-03 HGST Netherlands BV Read level grouping for increased flash performance
US10324648B1 (en) 2016-04-28 2019-06-18 Seagate Technology Llc Wear-based access optimization
US9971646B2 (en) 2016-06-01 2018-05-15 Apple Inc. Reading-threshold setting based on data encoded with a multi-component code
US10120585B2 (en) * 2016-08-10 2018-11-06 SK Hynix Inc. Memory system of optimal read reference voltage and operating method thereof
JP6659494B2 (ja) * 2016-08-19 2020-03-04 キオクシア株式会社 半導体記憶装置及びメモリシステム
US9953709B2 (en) 2016-09-06 2018-04-24 Toshiba Memory Corporation Semiconductor memory device and memory system
KR20180051272A (ko) * 2016-11-08 2018-05-16 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
CN110299177B (zh) * 2019-07-04 2021-01-19 合肥联诺科技有限公司 一种减小读操作电压抖动的电荷补偿电路及存储器结构
US11587627B2 (en) * 2021-04-16 2023-02-21 Micron Technology, Inc. Determining voltage offsets for memory read operations

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100408688B1 (ko) * 2001-10-23 2003-12-06 주식회사 하이닉스반도체 연산증폭기의 오프셋 전압을 보상하는 회로
US6956770B2 (en) * 2003-09-17 2005-10-18 Sandisk Corporation Non-volatile memory and method with bit line compensation dependent on neighboring operating modes
EP2067143B1 (en) * 2006-09-27 2014-01-08 SanDisk Technologies Inc. Memory with cell population distribution assisted read margining
KR100888842B1 (ko) * 2007-06-28 2009-03-17 삼성전자주식회사 읽기 전압을 최적화할 수 있는 플래시 메모리 장치 및그것의 독출 전압 설정 방법
US8117375B2 (en) * 2007-10-17 2012-02-14 Micron Technology, Inc. Memory device program window adjustment
WO2010039866A1 (en) * 2008-09-30 2010-04-08 Lsi Corporation Methods and apparatus for soft data generation for memory devices
JP4818381B2 (ja) * 2009-03-02 2011-11-16 株式会社東芝 半導体メモリ装置
KR101027501B1 (ko) * 2009-07-10 2011-04-06 쓰리에이로직스(주) Ｒｆ 리더, 이의 오프셋 전압 보상 방법 및 이를 포함하는 ｒｆ 시스템
US20110041005A1 (en) * 2009-08-11 2011-02-17 Selinger Robert D Controller and Method for Providing Read Status and Spare Block Management Information in a Flash Memory System
US8077515B2 (en) * 2009-08-25 2011-12-13 Micron Technology, Inc. Methods, devices, and systems for dealing with threshold voltage change in memory devices
KR101618311B1 (ko) * 2010-02-08 2016-05-04 삼성전자주식회사 플래시 메모리 장치 및 그것의 읽기 방법
US8467249B2 (en) * 2010-07-06 2013-06-18 Densbits Technologies Ltd. Systems and methods for storing, retrieving, and adjusting read thresholds in flash memory storage system
US8737136B2 (en) 2010-07-09 2014-05-27 Stec, Inc. Apparatus and method for determining a read level of a memory cell based on cycle information
KR101868332B1 (ko) * 2010-11-25 2018-06-20 삼성전자주식회사 플래시 메모리 장치 및 그것을 포함한 데이터 저장 장치

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