JP2017084436A5 - - Google Patents

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JP2017084436A5
JP2017084436A5 JP2016213142A JP2016213142A JP2017084436A5 JP 2017084436 A5 JP2017084436 A5 JP 2017084436A5 JP 2016213142 A JP2016213142 A JP 2016213142A JP 2016213142 A JP2016213142 A JP 2016213142A JP 2017084436 A5 JP2017084436 A5 JP 2017084436A5
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read threshold
threshold voltage
bit error
error rate
read
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JP2016213142A
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Japanese (ja)
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JP2017084436A (ja
JP6713909B2 (ja
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Priority claimed from US14/928,284 external-priority patent/US9818488B2/en
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JP2016213142A 2015-10-30 2016-10-31 装置、有形のマシン読取可能な記録可能な記憶媒体、および方法 Expired - Fee Related JP6713909B2 (ja)

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Application Number Priority Date Filing Date Title
US14/928,284 US9818488B2 (en) 2015-10-30 2015-10-30 Read threshold voltage adaptation using bit error rates based on decoded data
US14/928,284 2015-10-30

Publications (3)

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JP2017084436A JP2017084436A (ja) 2017-05-18
JP2017084436A5 true JP2017084436A5 (enExample) 2019-07-04
JP6713909B2 JP6713909B2 (ja) 2020-06-24

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JP2016213142A Expired - Fee Related JP6713909B2 (ja) 2015-10-30 2016-10-31 装置、有形のマシン読取可能な記録可能な記憶媒体、および方法

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US (1) US9818488B2 (enExample)
JP (1) JP6713909B2 (enExample)
KR (1) KR20170054276A (enExample)
CN (1) CN107039080B (enExample)

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