WO2022213320A1 - 用于闪存的数据恢复方法 - Google Patents

用于闪存的数据恢复方法 Download PDF

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WO2022213320A1
WO2022213320A1 PCT/CN2021/085938 CN2021085938W WO2022213320A1 WO 2022213320 A1 WO2022213320 A1 WO 2022213320A1 CN 2021085938 W CN2021085938 W CN 2021085938W WO 2022213320 A1 WO2022213320 A1 WO 2022213320A1
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read voltage
error rate
flash memory
check node
data
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PCT/CN2021/085938
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English (en)
French (fr)
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李前辉
王颀
杨柳
姜一扬
于晓磊
何菁
霍宗亮
叶甜春
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中国科学院微电子研究所
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Priority to PCT/CN2021/085938 priority Critical patent/WO2022213320A1/zh
Priority to US18/553,929 priority patent/US20240220355A1/en
Publication of WO2022213320A1 publication Critical patent/WO2022213320A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature

Definitions

  • the present disclosure relates to the field of non-volatile memory of semiconductor integrated circuits, and in particular, to a data recovery method for flash memory.
  • Flash memory is a kind of non-volatile memory, which is widely used in mobile phones, notebook computers, cloud storage and other storage fields.
  • the basic function of flash memory is to save data, and to ensure the consistency of written data and read data is Basic requirements for storage systems.
  • Error Control Code ECC, Error Correcting Code
  • ECC Error Correcting Code
  • the error control code also has a certain error correction range. If the original bit error rate of the read data is high, the error correction capability of the error control code will be exceeded, and the written data cannot be recovered correctly.
  • the flash memory In the process of data storage, the flash memory will be affected by the data retention noise. When the data is stored in the flash memory for a period of time, the charge stored in the flash memory storage unit will leak, and the threshold voltage distribution of the flash memory will tend to the lower threshold voltage. If one side is offset, if the read voltage used in the initial stage of data storage is used for the read operation, there will be a problem that the bit error rate of the read data exceeds the error correction capability of the error control code.
  • the present disclosure provides a data recovery method for a flash memory, including: reading data from the flash memory by using a preset read voltage; calculating a check node error rate corresponding to the data; and according to the check node error rate, Calculate the read voltage adjustment step size; adjust the preset read voltage according to the read voltage adjustment step size, use the adjusted preset read voltage to read data from the flash memory, and repeat the calculation for the corresponding data From the operation of the check node error rate to the operation of adjusting the preset read voltage according to the read voltage adjustment step size, until the check node error rate is the smallest; select the read voltage corresponding to the smallest check node error rate Data is read from the flash memory for data recovery.
  • the method further includes: judging whether the current error rate of the check node is less than a preset threshold; if so, stopping the adjustment of the preset read voltage according to the read voltage adjustment step, and using the adjusted read voltage.
  • the operation of reading data from the flash memory at a preset read voltage is performed with the currently read data for data recovery.
  • the method further includes: judging whether the current check node error rate is greater than the previous check node error rate, and if so, stopping the adjustment of the preset reading according to the read voltage adjustment step size. voltage, the operation of reading data from the flash memory by using the adjusted preset read voltage, and performing data recovery on the data read last time.
  • the calculating the check node error rate corresponding to the data includes: according to the formula:
  • R C sum(H ⁇ D k )/m
  • R C is the check node error rate
  • H is the parity check matrix
  • D k is the read data of one codeword
  • m is the number of check nodes.
  • the calculating the read voltage adjustment step size according to the check node error rate includes: establishing a functional relationship between the check node error rate and the bit error rate based on a threshold voltage distribution state of the flash memory. and the functional relationship between the bit error rate and the read voltage adjustment step size; according to the functional relationship between the check node error rate and the bit error rate, the bit error rate and the read voltage adjustment step size The functional relationship between the check node error rate and the read voltage adjustment step size is established; according to the functional relationship between the check node error rate and the read voltage adjustment step size, the read voltage adjustment step is calculated long.
  • the establishing a functional relationship between the check node error rate and the bit error rate and the functional relationship between the bit error rate and the read voltage adjustment step size includes: calculating a corresponding value of the preset read voltage.
  • the bit error rate of , wherein the calculating the bit error rate corresponding to the preset read voltage includes: according to the formula:
  • the i-th preset read voltage has the following relationship with the i-th optimal read voltage:
  • the i-th optimal read voltage is calculated by the following formula:
  • ⁇ i is the mean value of the i-th threshold voltage distribution state
  • ⁇ i is the variance of the i-th threshold voltage distribution state
  • ⁇ i-1 is the mean value of the i-1th threshold voltage distribution state
  • ⁇ i-1 is The variance of the i-1th threshold voltage distribution.
  • the method further includes: quantifying the functional relationship between the check node error rate and the read voltage adjustment step size into a look-up table, and obtaining the read voltage adjustment step size by looking up the look-up table.
  • the method further includes: establishing a read voltage adjustment step size between the ith preset read voltage and the ith optimal read voltage, and the jth preset read voltage and the jth preset read voltage.
  • the functional relationship between the read voltage adjustment steps between the optimal read voltages based on the functional relationship, calculated according to the read voltage adjustment step size between the i-th preset read voltage and the i-th optimal read voltage
  • the read voltage adjustment step size between the jth preset read voltage and the jth optimal read voltage is establishing a read voltage adjustment step size between the ith preset read voltage and the ith optimal read voltage, and the jth preset read voltage and the jth preset read voltage.
  • selecting a read voltage corresponding to a minimum check node error rate to read data from the flash memory to perform data recovery includes: performing data recovery on the read data by using an error control code.
  • FIG. 1 schematically shows a flowchart of a data recovery method for flash memory provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic flowchart of a method for calculating a read voltage adjustment step size according to the check node error rate according to an embodiment of the present disclosure
  • FIG. 3 schematically shows a threshold voltage distribution diagram of a NAND flash memory provided by an embodiment of the present disclosure
  • FIG. 4 schematically shows the i-th threshold voltage offset provided by the embodiment of the present disclosure and the jth threshold voltage offset There is a linear function relationship curve between them;
  • FIG. 5 schematically shows the threshold voltage distribution state diagram of the TLC NAND flash memory provided by the embodiment of the present disclosure
  • FIG. 6 schematically shows a graph of a functional relationship between the check node error rate and the read voltage adjustment step size provided by an embodiment of the present disclosure
  • FIG. 7 schematically shows a flowchart of a data recovery method for flash memory provided by another embodiment of the present disclosure.
  • FIG. 8 schematically shows a flowchart of a data recovery method for flash memory provided by another embodiment of the present disclosure
  • FIG. 9 schematically shows a graph of a monotonic function relationship between a check node error rate and a bit error rate provided by an embodiment of the present disclosure
  • FIG. 10 schematically shows a flowchart of a data recovery method for flash memory provided by another embodiment of the present disclosure.
  • Fig. 11 schematically shows a structural diagram of a data recovery system for flash memory provided by an embodiment of the present disclosure.
  • FIG. 1 schematically shows a flowchart of a data recovery method for flash memory provided by an embodiment of the present disclosure.
  • the method may include, for example, operations S101 to S105.
  • the preset read voltage is generally set as an initial read voltage, that is, an optimal read voltage with a data retention time of 0.
  • the read data may refer to the data written into the NAND flash memory after being encoded by the ECC, and the data read out when the storage system performs a read operation.
  • the read voltage adjustment step size is calculated according to the check node error rate and the bit error rate.
  • the read voltage adjustment step size may also be called a decision distance, which refers to the voltage value adjusted each time in the process of adjusting the initial read voltage to the optimum read voltage.
  • the preset read voltage is adjusted according to the read voltage adjustment step, and data is read from the flash memory using the adjusted preset read voltage, and the process returns to operation S102.
  • the judgment distance is calculated according to the error rate of the check node of the read data, and the judgment distance is used as the step size of the read voltage adjustment to adjust the read voltage, and a new read voltage is used after the read voltage is adjusted.
  • the read voltage can be used as the optimal read voltage, so that the step size of the read voltage adjustment can be dynamically adjusted, reducing the number of additional reads required to find the optimal read voltage, thereby reducing the time required for the search for the optimal read voltage in the re-reading error correction algorithm. .
  • a page may contain multiple code words.
  • each code word on a page is used.
  • the average value of the check node error rate is taken as the check node error rate of a page.
  • a method for calculating the check node error rate may be, for example:
  • R C sum(H ⁇ D k )/m
  • R C is the check node error rate
  • H is the parity check matrix
  • D k is the data of a codeword read, which is part of a page data read
  • m is the number of check nodes and the total number of rows in the H matrix.
  • FIG. 2 is a flowchart illustrating a method for calculating a read voltage adjustment step size according to the check node error rate according to an embodiment of the present disclosure.
  • FIG. 3 schematically shows a threshold voltage distribution diagram of a flash memory provided by an embodiment of the present disclosure.
  • the method may include, for example, operations S201 to S203.
  • operation S201 based on the threshold voltage distribution of the flash memory, a functional relationship between the check node error rate and the bit error rate and the functional relationship between the bit error rate and the read voltage adjustment step size are established.
  • the bit error rate of NAND flash memory is related to the read voltage, as shown in Figure 3, where,
  • the i-th initial read voltage is generally the best read voltage with a data retention time of 0.
  • the i-th optimal read voltage is the read voltage with the smallest bit error rate of the read data, and is also the intersection of the two threshold voltage distribution states after a period of data retention time, P i is the i-th threshold voltage distribution state, P i-1
  • the i-1th threshold voltage distribution state is the threshold voltage offset of the i-th threshold voltage distribution, is the threshold voltage offset of the i-1th threshold voltage distribution state, Adjust the step size for the read voltage between the ith preset read voltage and the ith optimal read voltage.
  • the dotted line part can represent the initial threshold voltage distribution of the flash memory.
  • move that is, move to the threshold voltage distribution state represented by the solid line part.
  • the area of the shaded part in FIG. 3 is the bit error rate of the read data of the NAND flash memory, and the area of the shaded part can be calculated by integrating the threshold voltage distribution. Therefore, the bit error rate between the two threshold voltage distribution states is also called the bit error rate under the i-th read voltage.
  • bit error rate corresponding to the preset read voltage needs to be calculated.
  • a method for calculating the bit error rate corresponding to the preset read voltage may be:
  • Calculate the bit error rate where P e is the bit error rate, i is the sequence number of the threshold voltage distribution state, is the i-th preset read voltage, ⁇ i is the mean value of the i-th threshold voltage distribution state of the flash memory, ⁇ i-1 is the average value of the i-1th threshold voltage distribution state of the flash memory, is the distribution function of the Gaussian distribution corresponding to the threshold voltage distribution state with a mean value of 0 and a variance of ⁇ i-1 .
  • the distribution function of the Gaussian distribution is the integral of the probability density of the Gaussian distribution, is the distribution function of a Gaussian distribution with a mean of 0 and a variance of ⁇ i .
  • the i-th preset read voltage has the following relationship with the i-th optimal read voltage:
  • the i-th optimal read voltage is calculated by:
  • ⁇ i is the mean value of the i-th threshold voltage distribution state
  • ⁇ i is the variance of the i-th threshold voltage distribution state
  • ⁇ i-1 is the mean value of the i-1th threshold voltage distribution state
  • ⁇ i-1 is The variance of the i-1th threshold voltage distribution.
  • the derivation process of the i-th optimal read voltage calculation formula is:
  • the threshold voltage distribution shown in Figure 3 is modeled as a Gaussian distribution, and the intersection of the two Gaussian distributions is the i-th optimal read voltage, which can be expressed as:
  • this embodiment uses the following formula for simplification:
  • the representation method of the i-th best read voltage can be expressed as:
  • Pe is the probability of a single bit error in the ECC codeword, and it is also the original bit error rate of the read data, and d i is the number of 1s in the i -th row of the H matrix.
  • H be a matrix with m rows and n columns. Therefore, the number of check equations in the ECC formed by the null space of the H matrix is m (that is, the number of check nodes in the Tanner graph is m) , then the average error probability of the m check equations is the check node error rate, which can be calculated by the following formula:
  • the i-th threshold voltage offset and the jth threshold voltage offset There is a linear function relationship between them, as follows:
  • a functional relationship between the check node error rate and the read voltage adjustment step size is established according to the functional relationship between the check node error rate and the bit error rate, and the functional relationship between the bit error rate and the read voltage adjustment step size.
  • the established functional relationship between the check node error rate and the read voltage adjustment step size is shown in FIG. 6 .
  • the read voltage adjustment step size is calculated according to the functional relationship between the check node error rate and the read voltage adjustment step size.
  • the functional relationship between the error rate of the check node and the read voltage adjustment step size can be quantified as a look-up table (Look Up Table, LUT), and the read voltage adjustment step size can be obtained by looking up the look-up table.
  • LUT Look Up Table
  • the error control code when selecting the read voltage corresponding to the minimum check node error rate to read data from the flash memory and perform data recovery, the error control code is used to perform data recovery on the read data.
  • FIG. 7 schematically shows a flowchart of a data recovery method for flash memory provided by another embodiment of the present disclosure.
  • the data recovery method provided in this embodiment may further include operations S701 to S702.
  • the difference between the jth preset read voltage and the jth optimum read voltage is calculated according to the read voltage adjustment step size between the ith preset read voltage and the ith optimum read voltage between read voltage adjustment steps.
  • TLC NAND flash memory the 7 read voltages of TLC NAND flash memory will be adjusted. Specifically, for Low Page, it needs to be adjusted according to calculate For Middle Page, it needs to be based on calculate and
  • the method can quickly adjust other read voltage adjustment steps based on one read voltage adjustment step.
  • FIG. 8 schematically shows a flowchart of a data recovery method for flash memory provided by another embodiment of the present disclosure.
  • the data recovery method provided in this embodiment may further include operations S801 to S802.
  • operation S802 is performed.
  • the relationship between the error rate of the check node and the bit error rate is a monotonic function. Therefore, the error rate of the check node can be used instead of the bit error rate, and the error rate of the check node can be replaced by the error rate of the check node.
  • the size of the read data is used to determine whether the read data can be corrected by ECC.
  • the check node error rate of the read data is less than a certain value, the read data errors can be corrected by ECC.
  • a check node error rate of less than 0.2338 can be corrected by ECC hard-decision decoding
  • a check node error rate of less than 0.3749 can be corrected by ECC soft-decision decoding.
  • operation S802 the adjustment of the preset read voltage according to the read voltage adjustment step is stopped, the operation of reading data from the flash memory by using the adjusted preset read voltage, and performing data recovery with the currently read data.
  • the data recovery method for flash memory provided by this embodiment is based on the aforementioned method of determining the judgment distance according to the check node error rate to adjust the read voltage, and adding judgment on whether the read data can be corrected by ECC.
  • the read voltage adjustment operation is stopped to improve system performance.
  • FIG. 10 schematically shows a flowchart of a data recovery method for flash memory provided by yet another embodiment of the present disclosure. As shown in FIG. 10 , the data recovery method provided in this embodiment may further include operations S1001 to S1002.
  • operation S1001 it is determined whether the current check node error rate is greater than the previous check node error rate.
  • the current check node error rate is greater than the previous check node error rate, indicating that the bit error rate of the current read data is increasing relative to the last time, and the read voltage of the last read data is the best read voltage. Therefore, in the current If the check node error rate is greater than the previous check node error rate, operation S1002 is performed.
  • operation S1002 the adjustment of the preset read voltage according to the read voltage adjustment step is stopped, and the operation of reading data from the flash memory using the adjusted preset read voltage is performed, and data recovery is performed on the data read last time.
  • the data recovery method for flash memory provided by this embodiment is based on the aforementioned method of determining the judgment distance according to the check node error rate to adjust the read voltage, and adding judgment on whether the read data can be corrected by ECC.
  • the read voltage adjustment operation is stopped to improve system performance.
  • FIG. 11 schematically shows a structural diagram of a data recovery system for flash memory provided by an embodiment of the present disclosure.
  • the system mainly includes:
  • the check node error rate calculation circuit (Cal_CNER) is used to calculate the check node error rate corresponding to the calculation data.
  • the table look-up circuit (Fun_CNER) for finding the decision distance according to the check node error rate is used to calculate the read voltage adjustment step size according to the check node error rate and bit error rate.
  • the table look-up circuit (Cal_RVDD) for the functional relationship between the i-th decision distance and the j-th decision distance is used to calculate the read voltage adjustment step size between the i-th preset read voltage and the i-th optimal read voltage to calculate the The read voltage adjustment step size between the j preset read voltages and the jth optimal read voltage.
  • check node is also called a check equation, which is a parity check equation formed by the position of 1 in each row of the check matrix of the ECC.
  • the concept of the check node error rate in the embodiment of the present disclosure includes both the concept of the check node error rate itself and the concept of the check equation. If the function relationship between the check equation and the decision distance is used to adjust the read voltage, All should be included within the protection scope of the present disclosure.

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Abstract

本公开涉及一种用于闪存的数据恢复方法，包括：采用预设读电压从闪存中读取数据；计算数据对应的校验节点出错率；根据校验节点出错率，计算读电压调整步长；根据读电压调整步长调整预设读电压，采用调整后的预设读电压从闪存中读取数据，并重复计算数据对应的校验节点出错率的操作至根据读电压调整步长调整预设读电压的操作，直至校验节点出错率最小；选择最小的校验节点出错率对应的读电压从闪存中读取数据，以进行数据恢复。该方法可动态调整读电压调整的步长，从而减小重读纠错算法中最佳读电压搜索所需要的时间，并且减少不必要地ECC译码，从而减小数据恢复所需要的时间。

Description

用于闪存的数据恢复方法 技术领域
本公开涉及半导体集成电路的非易失存储器领域，尤其涉及一种用于闪存的数据恢复方法。
背景技术
闪存尤其是NAND闪存是非挥发存储器的一种，被广泛的应用于手机、笔记本电脑、云存储等存储领域，闪存的基本功能是保存数据，保证写入的数据和读出的数据的一致性是存储系统的基本要求。差错控制编码(ECC，Error Correcting Code)可以纠正读出数据的错误，是保证写入数据和读出数据的一致性，提高存储系统可靠性的重要手段。但差错控制编码也有一定的纠错范围，如果读出数据的原始误码率较高，将会超出差错控制编码的纠错能力，无法正确的恢复出写入的数据。
在数据存储过程中，闪存会受到数据保持噪声的影响，当数据在闪存中存储一段时间后，存储在闪存储存单元的电荷将会泄漏，闪存的阈值电压分布态将会向阈值电压较小的一侧偏移，如果使用在数据存储初期使用的读电压进行读取操作，将会出现读出数据的误码率超过差错控制编码纠错能力的问题。
发明内容
本公开提供一种用于闪存的数据恢复方法，包括：采用预设读电压从所述闪存中读取数据；计算所述数据对应的校验节点出错率；根据所述校验节点出错率，计算读电压调整步长；根据所述读电压调整步长调整所述预设读电压，采用调整后的预设读电压从所述闪存中读取数据，并重复所述计算所述数据对应的校验节点出错率的操作至所述根据所述读电压调整步长调整所述预设读电压的操作，直至所述校验节点出错 率最小；选择最小的校验节点出错率对应的读电压从所述闪存中读取数据，以进行数据恢复。
可选地，所述方法还包括：判断当前所述校验节点出错率是否小于预设阈值；若是，停止所述根据所述读电压调整步长调整所述预设读电压，采用调整后的预设读电压从所述闪存中读取数据的操作，以当前读取的数据进行数据恢复。
可选地，所述方法还包括：判断当前所述校验节点出错率是否大于上一次所述校验节点出错率，若是，停止所述根据所述读电压调整步长调整所述预设读电压，采用调整后的预设读电压从所述闪存中读取数据的操作，以上一次读取的数据进行数据恢复。
可选地，其中，所述计算所述数据对应的校验节点出错率包括：根据公式：
R C＝sum(H·D k)/m
计算所述校验节点出错率，其中，R C为所述校验节点出错率，H为奇偶校验矩阵，D k为读出的一个码字的数据，m为校验节点的数量。
可选地，所述根据所述校验节点出错率，计算读电压调整步长包括：基于所述闪存的阈值电压分布态，建立所述校验节点出错率与所述误码率的函数关系以及所述误码率与所述读电压调整步长的函数关系；根据所述校验节点出错率与所述误码率的函数关系、所述误码率与所述读电压调整步长的函数关系，建立所述校验节点出错率与所述读电压调整步长的函数关系；根据所述校验节点出错率与所述读电压调整步长的函数关系，计算所述读电压调整步长。
可选地，所述建立所述校验节点出错率与所述误码率的函数关系以及所述误码率与所述读电压调整步长的函数关系包括：计算所述预设读电压对应的误码率，其中，所述计算所述预设读电压对应的误码率包括：根据公式：
Figure PCTCN2021085938-appb-000001
计算所述误码率，其中，P c为误码率，i为阈值电压分布态的序号，
Figure PCTCN2021085938-appb-000002
为 第i个预设读电压，μ i为所述闪存的第i个阈值电压分布态的均值，μ i-1为所述闪存的第i-1个阈值电压分布态的均值，
Figure PCTCN2021085938-appb-000003
为均值为0，方差为σ i-1的阈值电压分布态对应的高斯分布的分布函数，
Figure PCTCN2021085938-appb-000004
为均值为0，方差为σ i的高斯分布的分布函数。
可选地，其中，所述第i个预设读电压与第i个最佳读电压存在以下关系：
Figure PCTCN2021085938-appb-000005
其中，
Figure PCTCN2021085938-appb-000006
为第i个最佳读电压，
Figure PCTCN2021085938-appb-000007
为所述第i个预设读电压与所述第i个最佳读电压之间的读电压调整步长；
所述第i个最佳读电压通过下式计算：
Figure PCTCN2021085938-appb-000008
Figure PCTCN2021085938-appb-000009
其中，μ i为第i个阈值电压分布态的均值，σ i为第i个阈值电压分布态的方差，μ i-1为第i-1个阈值电压分布态的均值，σ i-1为第i-1个阈值电压分布态的方差。
可选地，所述方法还包括：将所述校验节点出错率与所述读电压调整步长的函数关系来量化为查找表，通过查找所述查找表得到所述读电压调整步长。
可选地，所述方法还包括：建立第i个预设读电压与所述第i个最佳读电压之间的读电压调整步长和第j个预设读电压与所述第j个最佳读电压之间的读电压调整步长之间的函数关系；基于函数关系，根据第i个预设读电压与所述第i个最佳读电压之间的读电压调整步长来计算第j个预设读电压与所述第j个最佳读电压之间的读电压调整步长。
可选地，选择最小的校验节点出错率对应的读电压从所述闪存中读取数据，以进行数据恢复包括：采用差错控制编码对读取的数据进行数据恢复。
附图说明
下面结合附图对本公开的具体实施方式作进一步详细的说明。
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需使用的附图作简单地介绍，显而易见，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图来获得其他的附图。
图1示意性示出了本公开实施例提供的用于闪存的数据恢复方法的流程图；
图2示意性本公开一实施例提供的根据所述校验节点出错率计算读电压调整步长的方法流程图；
图3示意性示出了本公开实施例提供的NAND闪存的阈值电压分布态图；
图4示意性示出了本公开实施例提供的第i个阈值电压偏移量
Figure PCTCN2021085938-appb-000010
和第j个阈值电压偏移量
Figure PCTCN2021085938-appb-000011
之间为线性函数关系曲线图；
图5示意性示出了本公开实施例提供的TLC NAND闪存的阈值电压分布态图
图6示意性示出了本公开实施例提供的校验节点出错率与读电压调整步长的函数关系曲线图；
图7示意性示出了本公开又一实施例提供的用于闪存的数据恢复方法的流程图；
图8示意性示出了本公开又一实施例提供的用于闪存的数据恢复方法的流程图；
图9示意性示出了本公开实施例提供的校验节点出错率和误码率之间的单调函数关系曲线图；
图10示意性示出了本公开又一实施例提供的用于闪存的数据恢复方法的流程图；
图11示意性示出了本公开实施例提供的用于闪存的数据恢复系统 的结构图。
具体实施方式
在下文中，本公开的示例性实施例将参照附图来详细描述。下面的实施例以举例的方式提供，以便充分传达本公开的精神给本公开所属领域的技术人员。因此，本公开不限于本文公开的实施例。
图1示意性示出了本公开一实施例提供的用于闪存的数据恢复方法的流程图。
如图1所示，该方法例如可以包括操作S101～S105。
在操作S101，采用预设读电压从闪存中读取数据。
该预设读电压一般设置为初始读电压，也即数据保持时间为0的最佳读电压。所指读出的数据可以指经过ECC编码后写入NAND闪存中的数据，在存储系统进行读操作时读出的数据。
在操作S102，计算数据对应的校验节点出错率。
在操作S103，根据校验节点出错率及误码率，计算读电压调整步长。
该读电压调整步长也可称作判决距离，指将初始读电压调整至最佳读电压过程中每次调整的电压数值。
在操作S104，根据读电压调整步长调整预设读电压，采用调整后的预设读电压从闪存中读取数据，并返回操作S102。
返回操作S102后，继续执行操作S102～S104，直至校验节点出错率最小。
在操作S105，选择最小的校验节点出错率对应的读电压从闪存中读取数据，以进行数据恢复。
上述实施例提供的数据恢复方法，根据读出数据的校验节点出错率来计算判决距离，并将判决距离作为读电压调整的步长对读电压进行调整，对读电压调整后采用新的读电压读出数据，并计算新的读电压的读出数据的校验节点出错率，并根据此校验节点出错率计算判决距离，循环往复此过程，并选取所对应的校验节点出错率最小的读电压作为最佳 读电压，从而可以动态调整读电压调整的步长，减少找到最佳读电压所需的额外读次数，进而减小重读纠错算法中最佳读电压搜索所需要的时间。
根据本公开的实施例，由于NAND闪存是以一个页(Page)为一个最小的读取单位，在实际工程应用中一个页上可能包含多个码字，本实例中采用一个页上各码字校验节点出错率的平均值作为一个页(Page)的校验节点出错率。具体的，一种计算校验节点出错率的方法例如可以为：
根据公式：
R C＝sum(H·D k)/m
计算校验节点出错率，其中，R C为校验节点出错率，H为奇偶校验矩阵，D k为读出的一个码字的数据，是读出的一个页(Page)数据的一部分，m为校验节点的数量，也是H矩阵的总行数。
图2示意性本公开一实施例提供的根据所述校验节点出错率计算读电压调整步长的方法流程图。
图3示意性示出了本公开实施例提供的闪存的阈值电压分布态图。
根据本公开的实施例，如图2所示，该方法例如可以包括操作S201～S203。在操作S201，基于闪存的阈值电压分布态，建立校验节点出错率与误码率的函数关系以及误码率与读电压调整步长的函数关系。
一般情况下，NAND闪存的误码率和读电压有关，如图3所示，其中，
Figure PCTCN2021085938-appb-000012
第i个初始读电压，一般是数据保持时间为0的最佳读电压，
Figure PCTCN2021085938-appb-000013
第i个最佳读电压，其为读出数据误码率最小的读电压，也是经过一段数据保持时间后的两个阈值电压分布态的交点，P i为第i个阈值电压分布态，P i-1第i-1个阈值电压分布态，
Figure PCTCN2021085938-appb-000014
为第i个阈值电压分布态的阈值电压偏移量，
Figure PCTCN2021085938-appb-000015
为第i-1个阈值电压分布态的阈值电压偏移量，
Figure PCTCN2021085938-appb-000016
为第i个预设读电压与第i个最佳读电压之间的读电压调整步长。虚线部分可以表示闪存的初始阈值电压分布态，当数据在闪存中存储一段时间后，存储在闪存储存单元的电荷将会泄漏，闪存的阈值电压分布态将会向阈值电压较小的一侧偏移，也即移动到实线部分所表示的阈值电压分布态。图3中阴影部分的面积即为NAND闪存读出数据的误码率， 阴影部分的面积可以用对阈值电压分布态做积分来求解。因此，两个阈值电压分布态之间的误码率，也叫第i个读电压下的误码率。
在建立函数关系的过程中需要计算预设读电压对应的误码率。请参阅图3，一种计算预设读电压对应的误码率的方法可以为：
根据公式：
Figure PCTCN2021085938-appb-000017
计算误码率，其中，P e为误码率，i为阈值电压分布态的序号，
Figure PCTCN2021085938-appb-000018
为第i个预设读电压，μ i为闪存的第i个阈值电压分布态的均值，μ i-1为闪存的第i-1个阈值电压分布态的均值，
Figure PCTCN2021085938-appb-000019
为均值为0，方差为σ i-1的阈值电压分布态对应的高斯分布的分布函数，高斯分布的分布函数是高斯分布的概率密度的积分，
Figure PCTCN2021085938-appb-000020
为均值为0，方差为σ i的高斯分布的分布函数。
其中，第i个预设读电压与第i个最佳读电压存在以下关系：
Figure PCTCN2021085938-appb-000021
Figure PCTCN2021085938-appb-000022
为第i个最佳读电压，
Figure PCTCN2021085938-appb-000023
为所述第i个预设读电压与所述第i个最佳读电压之间的读电压调整步长；
第i个最佳读电压通过下式计算：
Figure PCTCN2021085938-appb-000024
Figure PCTCN2021085938-appb-000025
其中，μ i为第i个阈值电压分布态的均值，σ i为第i个阈值电压分布态的方差，μ i-1为第i-1个阈值电压分布态的均值，σ i-1为第i-1个阈值电压分布态的方差。
具体的，第i个最佳读电压计算公式的推导过程为：
将图3所示的阈值电压分布态建模成高斯分布，两个高斯分布的交点就是第i个最佳读电压，用方程可以表示为：
Figure PCTCN2021085938-appb-000026
求解上述方程，当：
σ i-1≠σ i
可得到：
Figure PCTCN2021085938-appb-000027
Figure PCTCN2021085938-appb-000028
而，在实际NAND闪存中，由于：
σ i-1≈σ i
因此，本实施例使用如下公式进行简化：
Figure PCTCN2021085938-appb-000029
由此，第i个最佳读电压的表示方法可以表示为：
Figure PCTCN2021085938-appb-000030
Figure PCTCN2021085938-appb-000031
进一步地，建立校验节点出错率与误码率的函数关系：
在一个LDPC的校验矩阵H中，H中第i行中为1的bit组成了第i个奇偶校验方程，同时也是Tanner图中的第i个校验节点，第i个校验方程出错的概率R Ci可以用如下公式来计算：
Figure PCTCN2021085938-appb-000032
其中，P e是ECC码字中单个比特出错的概率，同时也是读出数据的原始误码率，d i是H矩阵的第i行中1的个数。
设H是一个m行n列的矩阵，因此，由该H矩阵的零空间所构成的ECC中的校验方程的个数为m(也就是在Tanner图中校验节点的个数是m)，那么这m个校验方程的平均错误概率，即为校验节点出错率，可以用如下公式计算：
Figure PCTCN2021085938-appb-000033
特例地，如果H矩阵每一行中1的个数都是相同的，也即d 1＝d 2＝…＝d m＝d，那么校验节点出错率可以简化为：
Figure PCTCN2021085938-appb-000034
基于上述计算，即可得到校验节点出错率与误码率的函数关系。
建立误码率与读电压调整步长的函数关系：
在本实施例中，如图4所示，第i个阈值电压偏移量
Figure PCTCN2021085938-appb-000035
和第j个阈值电压偏移量
Figure PCTCN2021085938-appb-000036
之间为线性函数关系，具体如下式：
Figure PCTCN2021085938-appb-000037
第i个读电压调整步长(判决距离)
Figure PCTCN2021085938-appb-000038
和第i个阈值电压偏移量
Figure PCTCN2021085938-appb-000039
之间为线性函数关系，具体如下式：
Figure PCTCN2021085938-appb-000040
根据上述两个线性关系，计算得到误码率与读电压调整步长的函数关系为：
Figure PCTCN2021085938-appb-000041
同理，如图5所示，对于TLC NAND闪存来说，对于Low Page的误码率与读电压调整步长的函数关系：
Figure PCTCN2021085938-appb-000042
对于Middle Page的误码率与读电压调整步长的函数关系：
Figure PCTCN2021085938-appb-000043
对于，Upper Page的误码率与读电压调整步长的函数关系：
Figure PCTCN2021085938-appb-000044
在操作S202，根据校验节点出错率与误码率的函数关系、误码率与读电压调整步长的函数关系，建立校验节点出错率与读电压调整步长的函数关系。
在本公开一实施例中，建立的校验节点出错率与读电压调整步长的函数关系如图6所示。
在操作S203，，根据校验节点出错率与读电压调整步长的函数关系，计算读电压调整步长。
可以将校验节点出错率与读电压调整步长的函数关系来量化为查找表(Look Up Table，LUT)，通过查找该查找表得到读电压调整步长。
基于上述校验节点出错率、误码率以及函数关系的计算方法，可保证每页数据对应的校验节点出错率及误码率的准确率，进而保证数据恢复精准度。
根据本公开的实施例，在选择最小的校验节点出错率对应的读电压从闪存中读取数据进行数据恢复时，采用差错控制编码对读取的数据进行数据恢复。
图7示意性示出了本公开又一实施例提供的用于闪存的数据恢复方法的流程图。
如图7所示，本实施例提供的数据恢复方法还可以包括操作S701～S702。
在操作S701，建立第i个预设读电压与第i个最佳读电压之间的读电压调整步长和第j个预设读电压与第j个最佳读电压之间的读电压调整步长之间的函数关系。
在操作S702，基于函数关系，根据第i个预设读电压与第i个最佳读电压之间的读电压调整步长来计算第j个预设读电压与第j个最佳读电压之间的读电压调整步长。
例如，对于TLC NAND闪存来说，将调整TLC NAND闪存的7个读电压，具体地，对于Low Page，需要根据
Figure PCTCN2021085938-appb-000045
计算
Figure PCTCN2021085938-appb-000046
对于Middle Page，需要根据
Figure PCTCN2021085938-appb-000047
计算
Figure PCTCN2021085938-appb-000048
和
Figure PCTCN2021085938-appb-000049
该方法可基于一读电压调整步长快速调整其它读电压调整步长。
图8示意性示出了本公开又一实施例提供的用于闪存的数据恢复方法的流程图。
如图8所示，本实施例提供的数据恢复方法还可以包括操作S801～S802。
在操作S801，判断当前校验节点出错率是否小于预设阈值。
若当前校验节点出错率小于预设阈值，则执行操作S802。
根据本公开的实施例，如图9所示，校验节点出错率和误码率之间为单调函数关系，因此，可以采用校验节点出错率代替误码率，使用校验节点出错率的大小来判断读出的数据能否被ECC纠正，当读出数据的校验节点出错率小于某个值时，读出的数据错误可以被ECC纠正。例如，在一具体示例中，校验节点出错率小于0.2338可以被ECC硬判决译码纠正，校验节点出错率小于0.3749，可以被ECC软判决译码纠正。
在操作S802，停止根据读电压调整步长调整预设读电压，采用调整后的预设读电压从闪存中读取数据的操作，以当前读取的数据进行数据恢复。
本实施例提供的用于闪存的数据恢复方法是在前述根据校验节点出错率确定判决距离从而进行读电压调整的方法的基础上，加入对读出数据能否被ECC纠错的判断，当判断读出的数据能够被ECC纠正时，停止读电压调整的操作，提高系统性能。
图10示意性示出了本公开又一实施例提供的用于闪存的数据恢复方法的流程图。如图10所示，本实施例提供的数据恢复方法还可以包括操作S1001～S1002。
在操作S1001，判断当前校验节点出错率是否大于上一次校验节点出错率。
当前校验节点出错率大于上一次校验节点出错率，表明当前读取数据的误码率相对一上一次在升高，上一次读取数据的读电压为最佳读电压，因此，在当前校验节点出错率大于上一次校验节点出错率，执行操作S1002。
在操作S1002，停止根据读电压调整步长调整预设读电压，采用调整后的预设读电压从闪存中读取数据的操作，以上一次读取的数据进行数据恢复。
本实施例提供的用于闪存的数据恢复方法是在前述根据校验节点出错率确定判决距离从而进行读电压调整的方法的基础上，加入对读出数据能否被ECC纠错的判断，当判断读出的数据能够被ECC纠正时，停止读电压调整的操作，提高系统性能。
图11示意性示出了本公开实施例提供的用于闪存的数据恢复系统的结构图。
如图11所示，该系统主要包括：
校验节点出错率计算电路(Cal_CNER)，用于计算计算数据对应的校验节点出错率。
根据校验节点出错率查找判决距离的查表电路(Fun_CNER)，用于根据校验节点出错率及误码率，计算读电压调整步长。
第i个判决距离和第j个判决距离的函数关系查表电路(Cal_RVDD)，用于根据第i个预设读电压与第i个最佳读电压之间的读电压调整步长来计算第j个预设读电压与第j个最佳读电压之间的读电压调整步长。
装置实施例未尽细节之处请参见方法实施例部分，此处不再赘述。
需要说明的是，校验节点也叫校验方程，是ECC的校验矩阵的每一行中为1的位置所组成的奇偶校验方程。本公开实施例中的校验节点出错率的概念，既包括校验节点出错率本身的概念，也包括校验方程的概念，如果使用校验方程和判决距离的函数关系来进行读电压调整，均应包含在本公开的保护范围之内。
尽管前面结合附图通过具体实施例对本公开进行了说明，但是，本领域技术人员容易认识到，上述实施例仅仅是示例性的，用于说明本公开的原理，其并不会对本公开的范围造成限制，本领域技术人员可以对上述实施例进行各种组合、修改和等同替换，而不脱离本公开的精神和范围。

Claims (10)

  1. 一种用于闪存的数据恢复方法，包括：
    采用预设读电压从所述闪存中读取数据；
    计算所述数据对应的校验节点出错率；
    根据所述校验节点出错率，计算读电压调整步长；
    根据所述读电压调整步长调整所述预设读电压，采用调整后的预设读电压从所述闪存中读取数据，并重复所述计算所述数据对应的校验节点出错率的操作至所述根据所述读电压调整步长调整所述预设读电压的操作，直至所述校验节点出错率最小；
    选择最小的校验节点出错率对应的读电压从所述闪存中读取数据，以进行数据恢复。
  2. 根据权利要求所述的用于闪存的数据恢复方法，所述方法还包括：
    判断当前所述校验节点出错率是否小于预设阈值；
    若是，停止所述根据所述读电压调整步长调整所述预设读电压，采用调整后的预设读电压从所述闪存中读取数据的操作，以当前读取的数据进行数据恢复。
  3. 根据权利要求1所述的用于闪存的数据恢复方法，所述方法还包括：
    判断当前所述校验节点出错率是否大于上一次所述校验节点出错率，
    若是，停止所述根据所述读电压调整步长调整所述预设读电压，采用调整后的预设读电压从所述闪存中读取数据的操作，以上一次读取的数据进行数据恢复。
  4. 根据权利要求1-3任一项所述的用于闪存的数据恢复方法，其中，所述计算所述数据对应的校验节点出错率包括：
    根据公式：
    R C＝sum(H·D k)/m
    计算所述校验节点出错率，其中，R C为所述校验节点出错率，H为奇偶校验矩阵，D k为读出的一个码字的数据，m为校验节点的数量。
  5. 根据权利要求1-3任一项所述的用于闪存的数据恢复方法，其中，所述根据所述校验节点出错率，计算读电压调整步长包括：
    基于所述闪存的阈值电压分布态，建立所述校验节点出错率与所述误码率的函数关系以及所述误码率与所述读电压调整步长的函数关系；
    根据所述校验节点出错率与所述误码率的函数关系、所述误码率与所述读电压调整步长的函数关系，建立所述校验节点出错率与所述读电压调整步长的函数关系；
    根据所述校验节点出错率与所述读电压调整步长的函数关系，计算所述读电压调整步长。
  6. 根据权利要求5所述的用于闪存的数据恢复方法，其中，所述建立所述校验节点出错率与所述误码率的函数关系以及所述误码率与所述读电压调整步长的函数关系包括：
    计算所述预设读电压对应的误码率，所述计算所述预设读电压对应的误码率包括：根据公式：
    Figure PCTCN2021085938-appb-100001
    计算所述误码率，其中，P e为误码率，i为阈值电压分布态的序号，
    Figure PCTCN2021085938-appb-100002
    为第i个预设读电压，μ i为所述闪存的第i个阈值电压分布态的均值，μi1为所述闪存的第i-1个阈值电压分布态的均值，
    Figure PCTCN2021085938-appb-100003
    为均值为0，方差为σ i-1的阈值电压分布态对应的高斯分布的分布函数，
    Figure PCTCN2021085938-appb-100004
    为均值为0，方差为σ i的高斯分布的分布函数。
  7. 根据权利要求6所述的用于闪存的数据恢复方法，其中，所述第i个预设读电压与第i个最佳读电压存在以下关系：
    Figure PCTCN2021085938-appb-100005
    其中，
    Figure PCTCN2021085938-appb-100006
    为第i个最佳读电压，
    Figure PCTCN2021085938-appb-100007
    为所述第i个预设读电压与所述第i个最佳读电压之间的读电压调整步长；
    所述第i个最佳读电压通过下式计算：
    Figure PCTCN2021085938-appb-100008
    Figure PCTCN2021085938-appb-100009
    其中，μ i为第i个阈值电压分布态的均值，σ i为第i个阈值电压分布态的方差，μ i-1为第i-1个阈值电压分布态的均值，σ i-1为第i-1个阈值电压分布态的方差。
  8. 根据权利要求5所述的用于闪存的数据恢复方法，其中，所述方法还包括：
    将所述校验节点出错率与所述读电压调整步长的函数关系来量化为查找表，通过查找所述查找表得到所述读电压调整步长。
  9. 根据权利要求7所述的用于闪存的数据恢复方法，其中，所述方法还包括：
    建立第i个预设读电压与所述第i个最佳读电压之间的读电压调整步长和第j个预设读电压与所述第j个最佳读电压之间的读电压调整步长之间的函数关系；
    基于函数关系，根据第i个预设读电压与所述第i个最佳读电压之间的读电压调整步长来计算第j个预设读电压与所述第j个最佳读电压之间的读电压调整步长。
  10. 根据权利要求1-3任一项所述的用于闪存的数据恢复方法，其中，选择最小的校验节点出错率对应的读电压从所述闪存中读取数据，以进行数据恢复包括：
    采用差错控制编码对读取的数据进行数据恢复。
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CN105913879A (zh) * 2015-02-23 2016-08-31 爱思开海力士有限公司 控制器、半导体存储系统及其操作方法
US20160372161A1 (en) * 2015-06-22 2016-12-22 SK Hynix Inc. Data storage device and operating method thereof
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