JP2014096448A - 半導体装置およびその製造方法 - Google Patents
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Abstract
【解決手段】半導体装置は、配線構造領域MCRと、発振子領域OCRとを備える。発振子領域OCRには、配線構造領域MCRの最上層金属配線上導電膜TOAと同一の層としての金属抵抗素子Rmを有する。発振子の抵抗体Rmとしての窒化チタンの薄膜と、バリアメタルとしての窒化チタンの薄膜とを同じ工程で形成することによりプロセスの短縮、コストの低減が可能となる。
【選択図】図10
Description
(実施の形態1)
まず一実施の形態の半導体装置の構成について、図1〜図5を用いて説明する。
図2を参照して、配線構造領域MCRには、たとえばMCUを含むいわゆる多層配線構造が形成されている。具体的には、配線構造領域MCRには、後述する配線層の金属配線A1〜ATが少なくとも1層(通常は複数の層)配置されている。ここでは金属配線A1〜A4および金属配線ATの5層形成されており、これら5層は互いに積層されて多層となるように配置されている。
図21を参照して、本実施の形態においては、実施の形態1と比較して、最上層の配線層MTを構成する最上層金属配線ATと、金属抵抗素子MRDの一部(金属抵抗素子層)と同一の層として形成される積層膜LM2(の一部)との間に挟まれるように、反射防止用絶縁膜ARFをさらに有している点において異なっている。この反射防止用絶縁膜ARFは、上記の下方反射防止膜BAと同様に、露光処理を行なう際の光の乱反射を抑制する機能を有する。
図23を参照して、図7と同様に通常のエッチング技術により配線構造領域MCRおよびガードリング形成領域GRRの一部に最上層金属配線ATのパターンが形成される。
図2および図21においては、コアトランジスタの形成領域のうち金属抵抗素子MRDが配置される領域は、他の領域に比べて層間絶縁膜II5の上面が下方に深く掘られている。これは図3のガードリング形成領域GRRにおいて層間絶縁膜II5の上面が下方に深く掘られ、発振子領域OCRにおいて積層膜LM2が配線構造領域MCRの積層膜LM1より下方に配置されるのと同様の理由(オーバーエッチング)に基づく。しかしオーバーエッチングの量が極めて少ない場合には、図27および図28に示すようにコアトランジスタの形成領域のうち金属抵抗素子MRDが配置される領域の層間絶縁膜II5の上面が他の領域の層間絶縁膜II5の上面とほとんど同じ高さになる。図27および図28に示す態様であっても、当該金属抵抗素子MRDが最上層金属配線ATの上面を覆う積層膜LM2と同一の層である限り、上記の実施の形態と同様の作用効果を奏する。
Claims (8)
- 主表面を有する半導体基板と、
前記半導体基板の前記主表面上に配置される、複数の層の金属配線を含む配線構造と、
前記配線構造の前記金属配線のうち最上層の最上層金属配線の上面を覆うように形成された最上層金属配線上導電膜と、
前記最上層金属配線上導電膜と同一の層で形成された金属抵抗素子とを備える、半導体装置。 - 前記金属抵抗素子は、前記最上層金属配線上導電膜より下方の位置に配置される、請求項1に記載の半導体装置。
- 前記配線構造が配置される配線構造領域と並ぶように前記主表面上に配置される発振子領域を備え、
前記配線構造領域と前記発振子領域との間にガードリング領域をさらに備える、請求項1に記載の半導体装置。 - 前記金属抵抗素子は、前記最上層金属配線と互いに離れて配置される、請求項1に記載の半導体装置。
- 前記最上層金属配線と前記最上層金属配線上導電膜との間に挟まれるように、反射防止用絶縁膜をさらに有する、請求項1に記載の半導体装置。
- 前記金属抵抗素子は窒化チタンにより構成される、請求項1に記載の半導体装置。
- 半導体基板を準備する工程と、
前記半導体基板の主表面上に複数の層の金属配線が形成される工程と、
前記金属配線のうちの最上層の最上層金属配線の上面から、前記最上層金属配線の下面に接して配置される層間絶縁膜まで延在する導電膜を形成する工程と、
前記導電膜をパターニングすることにより、前記導電膜を、前記最上層金属配線の上面を覆う最上層金属配線上導電膜と、前記最上層金属配線上導電膜と同一の層で形成される金属抵抗素子とに分離させる工程とを備える、半導体装置の製造方法。 - 前記最上層金属配線と前記最上層金属配線上導電膜との間に、反射防止用絶縁膜を形成する工程をさらに備える、請求項7に記載の半導体装置の製造方法。
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JP2012246458A JP6120528B2 (ja) | 2012-11-08 | 2012-11-08 | 半導体装置およびその製造方法 |
US14/070,949 US9099466B2 (en) | 2012-11-08 | 2013-11-04 | Semiconductor device and manufacturing method thereof |
US14/753,873 US9337142B2 (en) | 2012-11-08 | 2015-06-29 | Semiconductor device and manufacturing method thereof |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018116973A (ja) * | 2017-01-16 | 2018-07-26 | 富士通株式会社 | 配線構造、電子装置、及び、配線構造の製造方法 |
JP2019009345A (ja) * | 2017-06-27 | 2019-01-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2020155604A (ja) * | 2019-03-20 | 2020-09-24 | ローム株式会社 | 電子部品 |
Families Citing this family (7)
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US9659878B2 (en) | 2015-10-20 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level shielding in multi-stacked fan out packages and methods of forming same |
US10304772B2 (en) * | 2017-05-19 | 2019-05-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with resistive element |
US10985011B2 (en) | 2017-11-09 | 2021-04-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device with resistive elements |
US10672893B2 (en) | 2017-11-30 | 2020-06-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of making semiconductor device comprising flash memory and resulting device |
US10734298B2 (en) * | 2018-06-22 | 2020-08-04 | Microchip Technology Incorporated | Methods of reinforcing integrated circuitry of semiconductor devices and related semiconductor devices and packages |
US11171052B2 (en) * | 2019-04-29 | 2021-11-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of forming interconnect structures with selectively deposited pillars and structures formed thereby |
US11024533B2 (en) | 2019-05-16 | 2021-06-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of forming interconnect structures using via holes filled with dielectric film |
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2012
- 2012-11-08 JP JP2012246458A patent/JP6120528B2/ja active Active
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2013
- 2013-11-04 US US14/070,949 patent/US9099466B2/en active Active
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JPH10125676A (ja) * | 1996-10-15 | 1998-05-15 | Fujitsu Ltd | アルミニウム配線の作製方法 |
JPH11195711A (ja) * | 1997-10-27 | 1999-07-21 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JP2004055986A (ja) * | 2002-07-23 | 2004-02-19 | Internatl Business Mach Corp <Ibm> | 半導体装置の製造方法及びその半導体装置 |
JP2005235888A (ja) * | 2004-02-18 | 2005-09-02 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
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Cited By (4)
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JP2018116973A (ja) * | 2017-01-16 | 2018-07-26 | 富士通株式会社 | 配線構造、電子装置、及び、配線構造の製造方法 |
JP2019009345A (ja) * | 2017-06-27 | 2019-01-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2020155604A (ja) * | 2019-03-20 | 2020-09-24 | ローム株式会社 | 電子部品 |
JP7232679B2 (ja) | 2019-03-20 | 2023-03-03 | ローム株式会社 | 電子部品 |
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US9337142B2 (en) | 2016-05-10 |
US20140125421A1 (en) | 2014-05-08 |
US9099466B2 (en) | 2015-08-04 |
US20150303143A1 (en) | 2015-10-22 |
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