JP2014063725A - 機能性材料 - Google Patents
機能性材料 Download PDFInfo
- Publication number
- JP2014063725A JP2014063725A JP2013171259A JP2013171259A JP2014063725A JP 2014063725 A JP2014063725 A JP 2014063725A JP 2013171259 A JP2013171259 A JP 2013171259A JP 2013171259 A JP2013171259 A JP 2013171259A JP 2014063725 A JP2014063725 A JP 2014063725A
- Authority
- JP
- Japan
- Prior art keywords
- metal composite
- composite particles
- functional material
- electronic device
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B22—CASTING; POWDER METALLURGY
- B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
- B22F1/00—Metallic powder; Treatment of metallic powder, e.g. to facilitate working or to improve properties
- B22F1/09—Mixtures of metallic powders
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C1/00—Making non-ferrous alloys
- C22C1/04—Making non-ferrous alloys by powder metallurgy
- C22C1/0425—Copper-based alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/5328—Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/8182—Diffusion bonding
- H01L2224/81825—Solid-liquid interdiffusion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/8182—Diffusion bonding
- H01L2224/8183—Solid-solid interdiffusion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Conductive Materials (AREA)
- Powder Metallurgy (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Electrodes Of Semiconductors (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacture Of Metal Powder And Suspensions Thereof (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Dispersion Chemistry (AREA)
Abstract
【解決手段】本発明に係る機能性材料は、第1金属複合粒子、第2金属複合粒子及び第3金属複合粒子のうちの少なくとも2種を含有する。第1金属複合粒子、第2金属複合粒子及び第3金属複合粒子のそれぞれは、複数種の金属成分を含有している。第1金属複合粒子の融点T1(℃)と、第2金属複合粒子の融点T2(℃)と、第3金属複合粒子の融点T3(℃)とは、T1>T2>T3の関係を満たす。
【選択図】図1
Description
(a)カーケンダルボイド等を生じることなく、配線、電極、充填構造、封止構造、又は、接合構造を形成し得る機能性材料、及び、それを適用した電子デバイスを提供することができる。
(b)溶融温度が低く、凝固後は高い融点をもつ配線、電極、充填構造、封止構造、又は、接合構造を形成し得る機能性材料、及び、それを適用した電子デバイスを提供することができる。
第1金属複合粒子の具体例としては、Cuと、Si、B、Ti、AlまたはAgの群から選択された少なくとも一種とを含むものを挙げることができる。各組成分の組成比は、次のような範囲に設定することができる。
Sn:50wt%以下
Si、B、Ti、AlまたはAg:0.01wt%以下
Cu又はその合金粒子は、その表面が酸化抑制膜によって覆われていることが好ましい。酸化抑制膜としては、Cu又はその合金粒子の表面にメッキされたAgまたはSnのメッキ膜が適している、その他、150℃以上で昇華する樹脂の被膜であってもよい。
第2金属複合粒子の具体例としては、主成分たるSnと、Cuと、Si、B、Ti、AlまたはAgの群から選択された少なくとも一種とを含むものを挙げることができる。各組成分の組成比は、次のような範囲に設定することができる。
Cu:30wt%以下
Si、B、Ti、AlまたはAg:0.01wt%以下
(1)第3金属複合粒子は、一つの選択肢として、Snと、Biと、Gaと、Si、B、Ti、AlまたはAgの群から選択された少なくとも一種とを含むことができる。この場合の各組成分の組成比は、次のような範囲に設定することができる。
Bi:15〜60wt%
Ga:0.1wt%以下
Al:1wt%以下
Si、B、TiまたはAg:0.01wt%以下
Bi:Snに対して、20wt%以下
Sb:Snに対して、20wt%以下
Ga、Si、B、Ti、AlまたはAg:1wt%以下
上記具体例によれば、融点T1、T2、T3は、次のようになる。
T1=1100℃〜500℃
T2=400℃〜250℃
T3=250℃以下
52 柱状導体
53 電気絶縁層
71 基板
72 メタライズ配線
721 メタライズ層
73 電子部品
900 マザーボード
910 インターポーザ
921〜923 半導体チップ
931 接合材料
113 封止材料
Claims (6)
- 第1金属複合粒子、第2金属複合粒子及び第3金属複合粒子のうちの少なくとも2種を含有する機能性材料であって、
前記第1金属複合粒子、前記第2金属複合粒子及び前記第3金属複合粒子のそれぞれは、複数種の金属成分を含有しており、
第1金属複合粒子の融点T1(℃)と、第2金属複合粒子の融点T2(℃)と、第3金属複合粒子のT3(℃)とは、T1>T2>T3の関係を満たす、機能性材料。 - 第1金属複合粒子、第2金属複合粒子及び第3金属複合粒子のうちの少なくとも2種を含有する機能性材料であって、
前記第1金属複合粒子は、Cuと、Si、B、Ti、AlまたはAgの群から選択された少なくとも一種とを含んでおり、
前記第2金属複合粒子は、Snと、Cuと、Si、B、Ti、AlまたはAgの群から選択された少なくとも一種とを含んでおり、
前記第3金属複合粒子は、
(a)Snと、Biと、Gaと、Si、B、Ti、AlまたはAgの群から選択された少なくとも一種とを含むか、または、
(b)Snと、Biと、Inと、Sbと、Ga、Si、B、Ti、AlまたはAgの群から選択された少なくとも一種とを含む、
機能性材料。 - 請求項1または2に記載された機能性材料であって、前記第1金属複合粒子、前記第2金属複合粒子又は前記第3金属複合粒子を、流動性分散媒中に分散させたものでなる、機能性材料。
- 半導体基板と、柱状導体とを含む電子デバイスであって、
前記柱状導体は、請求項1乃至3の何れかに記載された機能性材料を用いて形成され、前記半導体基板に電気絶縁して充填されている、
電子デバイス。 - 請求項4に記載された電子デバイスであって、電子素子を含み、
前記電子素子は、配線導体、他の電子デバイス又は電子部品であって、その導体部分の少なくとも一部が、前記柱状導体の両端面の少なくとも一端面に拡散接合されている、
電子デバイス。 - 請求項5に記載された電子デバイスであって、前記柱状導体の両端面の少なくとも一端面に、ナノコンポジット構造合金ろう材又はナノコンポジット構造微粉末を用いて、他の導体を液相拡散接合または固相拡散接合させてある、電子デバイス。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013171259A JP5599497B2 (ja) | 2012-08-29 | 2013-08-21 | 機能性材料 |
US14/456,461 US9293416B2 (en) | 2012-08-29 | 2014-08-11 | Functional material |
EP14275173.4A EP2839904B1 (en) | 2013-08-21 | 2014-08-19 | Functional material |
CN201410415257.3A CN104425052B (zh) | 2013-08-21 | 2014-08-21 | 功能性材料 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012188908 | 2012-08-29 | ||
JP2012188908 | 2012-08-29 | ||
JP2013171259A JP5599497B2 (ja) | 2012-08-29 | 2013-08-21 | 機能性材料 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014063725A true JP2014063725A (ja) | 2014-04-10 |
JP5599497B2 JP5599497B2 (ja) | 2014-10-01 |
Family
ID=50618762
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013171259A Active JP5599497B2 (ja) | 2012-08-29 | 2013-08-21 | 機能性材料 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9293416B2 (ja) |
JP (1) | JP5599497B2 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016051843A (ja) * | 2014-09-01 | 2016-04-11 | 有限会社 ナプラ | 3次元積層配線基板、電子機器、情報処理システム、及び、情報通信システム |
JP2016171297A (ja) * | 2015-03-12 | 2016-09-23 | ソニー株式会社 | 固体撮像装置および製造方法、並びに電子機器 |
US9924592B2 (en) | 2016-08-18 | 2018-03-20 | Napra Co., Ltd. | Three-dimensional laminated circuit board, electronic device, information processing system, and information network system |
JP6357271B1 (ja) * | 2017-10-25 | 2018-07-11 | 有限会社 ナプラ | 柱状導体構造 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6042577B1 (ja) * | 2016-07-05 | 2016-12-14 | 有限会社 ナプラ | 多層プリフォームシート |
US10385469B2 (en) | 2017-09-11 | 2019-08-20 | Toyota Motor Engineering & Manufacturing North America, Inc. | Thermal stress compensation bonding layers and power electronics assemblies incorporating the same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002094242A (ja) * | 2000-09-14 | 2002-03-29 | Denso Corp | プリント多層基板の層間接続用材料およびこれを用いたプリント多層基板の製造方法 |
JP2002198654A (ja) * | 2000-12-25 | 2002-07-12 | Kyocera Corp | 電気素子内蔵配線基板およびその製造方法 |
JP2003101219A (ja) * | 2001-09-27 | 2003-04-04 | Kyocera Corp | 配線基板及びその製造方法 |
JP2004363052A (ja) * | 2003-06-06 | 2004-12-24 | Asahi Kasei Corp | 導電性材料、導電性成形体、導電性成形体の製造方法 |
JP2011023497A (ja) * | 2009-07-15 | 2011-02-03 | Napura:Kk | 回路基板及び電子デバイス |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5948533A (en) | 1990-02-09 | 1999-09-07 | Ormet Corporation | Vertically interconnected electronic assemblies and compositions useful therefor |
US5716663A (en) * | 1990-02-09 | 1998-02-10 | Toranaga Technologies | Multilayer printed circuit |
JP2967666B2 (ja) * | 1992-12-08 | 1999-10-25 | 株式会社村田製作所 | チップ型電子部品 |
US6207259B1 (en) * | 1998-11-02 | 2001-03-27 | Kyocera Corporation | Wiring board |
US6370013B1 (en) * | 1999-11-30 | 2002-04-09 | Kyocera Corporation | Electric element incorporating wiring board |
US7910837B2 (en) * | 2007-08-10 | 2011-03-22 | Napra Co., Ltd. | Circuit board, electronic device and method for manufacturing the same |
JP2012523091A (ja) | 2009-04-02 | 2012-09-27 | オーメット サーキッツ インク | 混合された合金フィラーを含む伝導性組成物 |
US8415784B2 (en) * | 2009-06-02 | 2013-04-09 | Napra Co., Ltd. | Electronic device, conductive composition, metal filling apparatus, and electronic device manufacturing method |
JP2012174332A (ja) | 2011-02-17 | 2012-09-10 | Fujitsu Ltd | 導電性接合材料、導体の接合方法、及び半導体装置の製造方法 |
JPWO2013038817A1 (ja) | 2011-09-16 | 2015-03-26 | 株式会社村田製作所 | 導電性材料、それを用いた接続方法、および接続構造 |
JP5124693B1 (ja) | 2012-04-24 | 2013-01-23 | 有限会社 ナプラ | 電子機器 |
-
2013
- 2013-08-21 JP JP2013171259A patent/JP5599497B2/ja active Active
-
2014
- 2014-08-11 US US14/456,461 patent/US9293416B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002094242A (ja) * | 2000-09-14 | 2002-03-29 | Denso Corp | プリント多層基板の層間接続用材料およびこれを用いたプリント多層基板の製造方法 |
JP2002198654A (ja) * | 2000-12-25 | 2002-07-12 | Kyocera Corp | 電気素子内蔵配線基板およびその製造方法 |
JP2003101219A (ja) * | 2001-09-27 | 2003-04-04 | Kyocera Corp | 配線基板及びその製造方法 |
JP2004363052A (ja) * | 2003-06-06 | 2004-12-24 | Asahi Kasei Corp | 導電性材料、導電性成形体、導電性成形体の製造方法 |
JP2011023497A (ja) * | 2009-07-15 | 2011-02-03 | Napura:Kk | 回路基板及び電子デバイス |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016051843A (ja) * | 2014-09-01 | 2016-04-11 | 有限会社 ナプラ | 3次元積層配線基板、電子機器、情報処理システム、及び、情報通信システム |
JP2016171297A (ja) * | 2015-03-12 | 2016-09-23 | ソニー株式会社 | 固体撮像装置および製造方法、並びに電子機器 |
US9924592B2 (en) | 2016-08-18 | 2018-03-20 | Napra Co., Ltd. | Three-dimensional laminated circuit board, electronic device, information processing system, and information network system |
JP6357271B1 (ja) * | 2017-10-25 | 2018-07-11 | 有限会社 ナプラ | 柱状導体構造 |
JP2019079965A (ja) * | 2017-10-25 | 2019-05-23 | 有限会社 ナプラ | 柱状導体構造 |
Also Published As
Publication number | Publication date |
---|---|
JP5599497B2 (ja) | 2014-10-01 |
US20150054158A1 (en) | 2015-02-26 |
US9293416B2 (en) | 2016-03-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5599497B2 (ja) | 機能性材料 | |
JP5885351B2 (ja) | 接合部及び電気配線 | |
US9741664B2 (en) | High density substrate interconnect formed through inkjet printing | |
CN104064551B (zh) | 一种芯片堆叠封装结构和电子设备 | |
KR102600004B1 (ko) | 반도체 패키지 | |
JP6029222B1 (ja) | 金属粒子、ペースト、成形体、及び、積層体 | |
US11128268B1 (en) | Power amplifier packages containing peripherally-encapsulated dies and methods for the fabrication thereof | |
TWI809190B (zh) | 半導體封裝 | |
CN110880486A (zh) | 扇出型半导体封装件 | |
JP5709719B2 (ja) | 電子部品支持装置及び電子デバイス | |
JP2009044065A (ja) | 基板配線用導電性組成物、回路基板及び電子デバイス | |
JPH08330506A (ja) | 回路基板構造 | |
JP4902773B2 (ja) | 半導体デバイス | |
EP2839904B1 (en) | Functional material | |
JP2011114317A (ja) | 回路基板及び電子デバイス | |
JP2008124072A (ja) | 半導体装置 | |
JP5822977B2 (ja) | 電子デバイス、その製造方法、金属粒子及び導電性ペースト | |
JP2012174826A (ja) | 電子デバイス及びその製造方法 | |
WO2018168185A1 (ja) | 半導体装置 | |
TWI652783B (zh) | 半導體裝置及其製造方法 | |
US9515044B1 (en) | Electronic device, method of manufacturing the same, metal particle, and electroconductive paste | |
WO2023233591A1 (ja) | 半導体装置および半導体装置の製造方法 | |
JP2009218287A (ja) | スルーホール充填基板およびその製造方法 | |
TWI273692B (en) | Semiconductor package and method for manufacturing the same | |
JP2011166066A (ja) | 電子デバイスの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20140326 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140605 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20140612 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140730 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140812 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5599497 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |