JP2013539952A - 3レベルdac要素を有するパイプラインadc - Google Patents
3レベルdac要素を有するパイプラインadc Download PDFInfo
- Publication number
- JP2013539952A JP2013539952A JP2013534018A JP2013534018A JP2013539952A JP 2013539952 A JP2013539952 A JP 2013539952A JP 2013534018 A JP2013534018 A JP 2013534018A JP 2013534018 A JP2013534018 A JP 2013534018A JP 2013539952 A JP2013539952 A JP 2013539952A
- Authority
- JP
- Japan
- Prior art keywords
- coupled
- decoder
- current source
- base
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 claims description 7
- 229920005994 diacetyl cellulose Polymers 0.000 description 2
- 238000009795 derivation Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/904,688 US8269661B2 (en) | 2010-10-14 | 2010-10-14 | Pipelined ADC having a three-level DAC elements |
| US12/904,688 | 2010-10-14 | ||
| PCT/US2011/056256 WO2012051478A2 (en) | 2010-10-14 | 2011-10-14 | Pipelined adc having three-level dac elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2013539952A true JP2013539952A (ja) | 2013-10-28 |
| JP2013539952A5 JP2013539952A5 (enExample) | 2014-11-13 |
Family
ID=45933680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013534018A Pending JP2013539952A (ja) | 2010-10-14 | 2011-10-14 | 3レベルdac要素を有するパイプラインadc |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8269661B2 (enExample) |
| JP (1) | JP2013539952A (enExample) |
| CN (1) | CN103155416B (enExample) |
| WO (1) | WO2012051478A2 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017046058A (ja) * | 2015-08-24 | 2017-03-02 | 株式会社東芝 | Ad変換器、アナログフロントエンド、及びセンサシステム |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8571137B2 (en) * | 2011-01-14 | 2013-10-29 | Broadcom Corporation | Distortion and aliasing reduction for digital to analog conversion |
| US8872685B2 (en) * | 2013-03-15 | 2014-10-28 | Qualcomm Incorporated | Techniques to reduce harmonic distortions of impedance attenuators for low-power wideband high-resolution DACs |
| US9397676B1 (en) | 2015-09-29 | 2016-07-19 | Analog Devices, Inc. | Low power switching techniques for digital-to-analog converters |
| CN106788432B (zh) | 2016-12-30 | 2020-09-22 | 华为技术有限公司 | 数模转换电路 |
| US10868557B2 (en) * | 2018-03-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd | Analog to digital converter with current steering stage |
| CN108988861B (zh) * | 2018-08-06 | 2021-10-08 | 中国电子科技集团公司第二十四研究所 | 电流模余量放大器 |
| US10784878B1 (en) * | 2019-12-21 | 2020-09-22 | Steradian Semiconductors Private Limited | Digital to analog converter tolerant to element mismatch |
| US11042368B1 (en) | 2019-12-31 | 2021-06-22 | Express Scripts Strategic Development, Inc. | Scalable software development and deployment system using inversion of control architecture |
| US10819365B1 (en) | 2020-02-06 | 2020-10-27 | Analog Devices, Inc. | Utilizing current memory property in current steering digital-to-analog converters |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03192922A (ja) * | 1989-12-22 | 1991-08-22 | Nec Corp | 3値論理回路 |
| JP2000236251A (ja) * | 1998-12-15 | 2000-08-29 | Nec Corp | 3値スイッチ回路 |
| JP2001525627A (ja) * | 1997-12-02 | 2001-12-11 | マキシム・インテグレーテッド・プロダクツ・インコーポレーテッド | パイプライン接続型アナログ‐ディジタル変換器における効率的な誤差補正 |
| JP2002009622A (ja) * | 2000-06-16 | 2002-01-11 | Nec Yonezawa Ltd | 電流加算型dac |
| JP2004274798A (ja) * | 1997-01-30 | 2004-09-30 | Fujitsu Ltd | 容量結合を利用したad変換回路及びda変換回路 |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6081218A (en) | 1998-01-30 | 2000-06-27 | Lucent Technologies, Inc. | Five-level switched-capacitor DAC, method of operation thereof and sigma-delta converter employing the same |
| US6195032B1 (en) * | 1999-08-12 | 2001-02-27 | Centillium Communications, Inc. | Two-stage pipelined recycling analog-to-digital converter (ADC) |
| US6587060B1 (en) | 1999-08-26 | 2003-07-01 | Duane L. Abbey | Multi-bit monotonic quantizer and linearized delta-sigma modulator based analog-to-digital and digital-to analog conversion |
| WO2001067614A1 (en) * | 2000-02-22 | 2001-09-13 | The Regents Of The University Of California | Digital cancellation of d/a converter noise in pipelined a/d converters |
| US6373418B1 (en) | 2000-05-25 | 2002-04-16 | Rockwell Collins, Inc. | Nyquist response restoring delta-sigma modulator based analog to digital and digital to analog conversion |
| US6369744B1 (en) | 2000-06-08 | 2002-04-09 | Texas Instruments Incorporated | Digitally self-calibrating circuit and method for pipeline ADC |
| US6441765B1 (en) * | 2000-08-22 | 2002-08-27 | Marvell International, Ltd. | Analog to digital converter with enhanced differential non-linearity |
| EP1465347B9 (en) | 2003-03-31 | 2007-11-14 | AMI Semiconductor Belgium BVBA | Monotonic precise current DAC |
| JP3765797B2 (ja) * | 2003-05-14 | 2006-04-12 | 沖電気工業株式会社 | パイプライン型アナログ・ディジタル変換器 |
| US7289055B2 (en) * | 2004-02-05 | 2007-10-30 | Sanyo Electric Co., Ltd. | Analog-digital converter with gain adjustment for high-speed operation |
| US7280064B2 (en) * | 2005-09-08 | 2007-10-09 | Realtek Semiconductor Corp. | Pipeline ADC with minimum overhead digital error correction |
| US7688238B2 (en) * | 2007-03-27 | 2010-03-30 | Slicex, Inc. | Methods and systems for calibrating a pipelined analog-to-digital converter |
| DE602007007346D1 (de) * | 2007-11-27 | 2010-08-05 | Seda De Barcelona Sa | Vorrichtung zur Sortierung und Ausrichtung von Vorformen |
| JP2009177446A (ja) * | 2008-01-24 | 2009-08-06 | Oki Semiconductor Co Ltd | パイプライン型アナログ・デジタル変換器 |
| EP2237424B1 (en) | 2009-03-30 | 2013-02-27 | Dialog Semiconductor GmbH | Tri-level dynamic element matcher allowing reduced reference loading and DAC element reduction |
-
2010
- 2010-10-14 US US12/904,688 patent/US8269661B2/en active Active
-
2011
- 2011-10-14 JP JP2013534018A patent/JP2013539952A/ja active Pending
- 2011-10-14 WO PCT/US2011/056256 patent/WO2012051478A2/en not_active Ceased
- 2011-10-14 CN CN201180049508.5A patent/CN103155416B/zh active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03192922A (ja) * | 1989-12-22 | 1991-08-22 | Nec Corp | 3値論理回路 |
| JP2004274798A (ja) * | 1997-01-30 | 2004-09-30 | Fujitsu Ltd | 容量結合を利用したad変換回路及びda変換回路 |
| JP2001525627A (ja) * | 1997-12-02 | 2001-12-11 | マキシム・インテグレーテッド・プロダクツ・インコーポレーテッド | パイプライン接続型アナログ‐ディジタル変換器における効率的な誤差補正 |
| JP2000236251A (ja) * | 1998-12-15 | 2000-08-29 | Nec Corp | 3値スイッチ回路 |
| JP2002009622A (ja) * | 2000-06-16 | 2002-01-11 | Nec Yonezawa Ltd | 電流加算型dac |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017046058A (ja) * | 2015-08-24 | 2017-03-02 | 株式会社東芝 | Ad変換器、アナログフロントエンド、及びセンサシステム |
Also Published As
| Publication number | Publication date |
|---|---|
| US20120092199A1 (en) | 2012-04-19 |
| US8269661B2 (en) | 2012-09-18 |
| WO2012051478A3 (en) | 2012-06-14 |
| CN103155416A (zh) | 2013-06-12 |
| WO2012051478A2 (en) | 2012-04-19 |
| CN103155416B (zh) | 2016-03-30 |
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