WO2012051478A2 - Pipelined adc having three-level dac elements - Google Patents

Pipelined adc having three-level dac elements Download PDF

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Publication number
WO2012051478A2
WO2012051478A2 PCT/US2011/056256 US2011056256W WO2012051478A2 WO 2012051478 A2 WO2012051478 A2 WO 2012051478A2 US 2011056256 W US2011056256 W US 2011056256W WO 2012051478 A2 WO2012051478 A2 WO 2012051478A2
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WO
WIPO (PCT)
Prior art keywords
coupled
current source
decoder
predriver
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2011/056256
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English (en)
French (fr)
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WO2012051478A3 (en
Inventor
Marco Corsi
Robert F. Payne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Japan Ltd
Texas Instruments Inc
Original Assignee
Texas Instruments Japan Ltd
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Japan Ltd, Texas Instruments Inc filed Critical Texas Instruments Japan Ltd
Priority to CN201180049508.5A priority Critical patent/CN103155416B/zh
Priority to JP2013534018A priority patent/JP2013539952A/ja
Publication of WO2012051478A2 publication Critical patent/WO2012051478A2/en
Publication of WO2012051478A3 publication Critical patent/WO2012051478A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal

Definitions

  • ADCs analog-to-digital converters
  • DAC digital-to-analog converter
  • FIG. 1 illustrates an example of a conventional pipelined ADC 100.
  • ADC 100 generally comprises a pipeline (which receives an analog input signal AIN) that provides digital signals to a digital output circuit 106 so that a digital output signal DOUT can be generated.
  • the pipeline is generally comprised of a buffer 108, output ADC 104, and ADC stages 102-1 to 102-N (which are generally arranged in a sequence).
  • Each of the ADC stages 102-1 to 102-N generally comprises a track-and-hold (T/H) circuit 112, a sub-ADC 118, DAC 120, and a residue amplifier 122.
  • T/H track-and-hold
  • T/H circuit 112 for each ADC stage 102-1 to 102-N, receives an input signal (i.e., signal AIN or the residue from the previous stage) and samples the signal based on clock signal CLK.
  • Sub- ADC 118 (which also uses the clock signal CLK) converts the sample to a digital signal, which is provided to digital output circuit 106 and DAC 120.
  • Residue amplifier 122 then amplifies the difference between the sampled signal (from T/H circuit 112) and the output from DAC 120, which is the residue signal or residue of the stage.
  • the final ADC stage 102- N of the sequence then provides its residue to output ADC 104, which provides a digital signal to digital output circuit 106.
  • FIG. 2 shows a more detailed example of DAC 120n.
  • sub-ADC sub-ADC
  • control word 118 is a coarse ADC having 2 n levels, which can provide a control word to the DAC 120.
  • This control word can be thermometer coded with 2 n levels and can be used to control DAC switches 202-1 to 202-R (where each switch 202-1 to 202-R can generate a "+1" or "-1").
  • control signals (which are generally derived from the control word) can be provided to transistors QUI to QUR and QDl to QDR so as to enable current to be sourced through the or paths (through the respective current source 204-1 to 204- R).
  • a problem is that, regardless of the code for DAC 120, the noise from the current sources 204-1 to 204-R can be observed at the output of residue amplifier 122.
  • An example embodiment implementing principles of the invention takes the form of an apparatus with a logic circuit that includes a decoder that receives a control word and that generates a plurality of control signals from the control word; a plurality of predrivers that are each coupled to the decoder so as to receive at least one of the control signals; and a plurality of three-state digital-to-analog converter (DAC) switches, wherein each three-state DAC is coupled to at least one of the predrivers.
  • DAC digital-to-analog converter
  • each of the plurality of three-state DAC switches further comprises: a current source; a first transistor that is coupled to the current source and an associated predriver, wherein the associated predriver controls the first transistor; a second transistor that is coupled to the current source and the associated predriver, wherein the associated predriver controls the second transistor; and a third transistor that is coupled between the current source and ground and that is coupled to the associated predriver, wherein the associated predriver controls the third transistor.
  • the first second and third transistors are NPN transistors, and wherein each of the first, second, and third transistors is coupled to the current source at emitter and to the associated predriver at its base.
  • each predriver further compromises: a first current source; a second current source; a first cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder; and a second cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder.
  • the first cascaded set further comprises: a first bipolar transistor that is coupled to the decoder at its base and to an associated three-state DAC switch at its collector; a second bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector; a third bipolar transistor that is coupled to the decoder at its base, to the emitters of the first and second bipolar transistors at its collector, and to the first current source at its emitter; and a fourth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the first current source at its emitter.
  • the second cascaded set further comprises: a fifth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector; a sixth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector; a seventh bipolar transistor that is coupled to the decoder at its base, to the emitters of the fifth and sixth bipolar transistors at its collector, and to the second current source at its emitter; and an eighth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the second current source at its emitter.
  • an apparatus comprises a digital output circuit; a pipeline having a plurality of analog-to-digital converter (ADC) stages that are coupled in together in a sequence, wherein each ADC stage includes: a track-and-hold (T/H) circuit; a sub-ADC that is coupled to the T/H circuit and to the digital output circuit; a DAC that is coupled to the sub-ADC, wherein the DAC includes: a decoder that is coupled to the sub- ADC; a plurality of predrivers that are each coupled to the decoder; and a plurality of three-state DAC switches, wherein each three-state DAC is coupled to at least one of the predrivers; and a residue amplifier that is coupled to the DAC and the T/H circuit.
  • ADC analog-to-digital converter
  • the pipeline further comprises: a buffer that receives an analog input signal and that is coupled to the first ADC stage of the sequence; and a plurality of output ADCs that are each coupled to the last ADC stage of the sequence and to the digital output circuit.
  • an apparatus comprises a digital output circuit that generates a digital output signal; a buffer that receives an analog input signal; a plurality of ADC stages that are coupled in together in a sequence, the first ADC stage of the sequence is coupled to the buffer, and wherein each ADC stage includes: a T/H circuit; a sub- ADC that is coupled to the T/H circuit and to the digital output circuit; a DAC that is coupled to the sub-ADC, wherein the DAC includes: a decoder that is coupled to the sub-ADC; a plurality of predrivers, wherein each predriver includes: a first current source; a second current source; a first cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder; a second cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder; and a plurality of three-state DAC switches, wherein each three-state DAC
  • the first second and third transistors are bipolar transistors, and wherein each of the first, second, and third transistors is coupled to the current source at emitter and to the associated predriver at its base.
  • the first cascaded set further comprises: a first bipolar transistor that is coupled to the decoder at its base and to an associated three-state DAC switch at its collector; a second bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector; a third bipolar transistor that is coupled to the decoder at its base, to the emitters of the first and second bipolar transistors at its collector, and to the first current source at its emitter; and a fourth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the first current source at its emitter.
  • the second cascaded set further comprises: a fifth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector; a sixth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector; a seventh bipolar transistor that is coupled to the decoder at its base, to the emitters of the fifth and sixth bipolar transistors at its collector, and to the second current source at its emitter; and an eighth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the second current source at its emitter.
  • FIG. 1 illustrates an example of a conventional pipelined ADC
  • FIG. 2 is a diagram of an example of a DAC of FIG. 1;
  • FIG. 3 illustrates an example of a DAC in accordance with an example embodiment of the invention
  • FIG. 4 illustrates an example of a three-state DAC switch of FIG. 3
  • FIG. 5 illustrates an example of the logic circuitry of FIG. 3.
  • FIG. 6 illustrates an example of a predriver of FIG. 5.
  • FIGS. 3 and 4 illustrate a digital-to-analog converter (DAC) 300 in accordance with an example embodiment of the invention.
  • the DAC 300 generally comprises logic circuitry 304 and three-state DAC switches 302-1 to 302-k.
  • the logic circuitry 304 can receive a control word from ADC 118 and can generate control signals (i.e., control signals P, M, and C shown in FIG. 4) for each of the three-state switches 302-1 to 302-k.
  • control signals P, M, and C shown in FIG. 4 for each of the three-state switches 302-1 to 302-k.
  • each three-state DAC switch 302-1 to 302-k includes transistors QU QD, QG (which can be NPN transistors) and a current source 402 so that, based on the control signals P, M, and C, the three-state DAC switch 302 can generate a "+1", "-1", or "0" as shown in Table 1 below.
  • the logic circuitry 304 can employ decoder 504 and predrivers 502-1 to 502-k of FIG. 5.
  • the decoder 504 generally receives a control word so as to generate control signals (i.e., two) for predrivers 502-1 to 502-k.
  • Each predriver 502-1 to 502-k (as shown in this example) outputs three control signals PI /Ml /CI to Pk/Mk/Ck, which generally corresponds to the signal P, M, and C (as shown in FIG. 4).
  • FIG. 6 illustrates an example implementation of predrivers 502-1 to 502-k
  • predriver 502 generally comprises sets of cascaded differential pairs of transistors Ql through Q4 and Q5 through Q8 (which can be NPN transistors), current sources 602-1 and 602-2, and resistors Rl through R3.
  • control signals INI and IN2 can be provided by decoder 504 with inverted control signals INI and IN 2 being generated by inverters 606 and 608; alternatively, inverted control signals INI and IN 2 can be provided by decoder 504.
  • control signal INI and inverted control signal INI are provided to differential pairs Q1/Q2 and Q5/Q8, while control signal IN2 and inverted control signal IN 2 are provided to differential pairs Q3/Q4 and Q6/Q7.
  • the predriver 502 can generate the control signals P, M, and C shown in Table 1 above. As an illustration, the derivation of control signals P, M, and C from control signals INI and IN2 for predriver 502 can be seen in Table 2 below.
  • a reason for using this DAC 300 is that transistor QG (for each switch 302-1 to 303-k) enables a reduction in noise contribution from current source 402 (for each switch 302-1 to 303-k) for a significant portion of the transfer response. For example, with DAC 120, there would be a noise contribution from each current source 204-1 to 204-R for a 0V output, but, with DAC 300, there would be no noise contribution from current source 402 (from any of switches 302-1 to 203-k) for a 0V output.
  • 2 n_1 three-state DAC switches (i.e., 302-1) could be used in DAC 300 instead of 2 n DAC switches (i.e., 202-1) in DAC 120, which results in a reduction in area.
  • each of DAC 120 and 300 has a total of 15 states (ranging from -7 to 7). As can clearly be seen, there are 14 DAC switches (labeled 202-1 to 202-14) used for DAC 120, whereas there are 7 three-state DAC switches (labeled 302-1 to 302-7) used for DAC.
  • DAC switch 302-6 -1 -1 -1 0 0 0 0 0 0 0 0 0 0 1 1 1
  • DAC switch 302-7 -1 0 0 0 0 0 0 0 0 0 0 0 0 1

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
PCT/US2011/056256 2010-10-14 2011-10-14 Pipelined adc having three-level dac elements Ceased WO2012051478A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201180049508.5A CN103155416B (zh) 2010-10-14 2011-10-14 具有三级dac元件的流水线结构的adc
JP2013534018A JP2013539952A (ja) 2010-10-14 2011-10-14 ３レベルｄａｃ要素を有するパイプラインａｄｃ

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/904,688 US8269661B2 (en) 2010-10-14 2010-10-14 Pipelined ADC having a three-level DAC elements
US12/904,688 2010-10-14

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WO2012051478A2 true WO2012051478A2 (en) 2012-04-19
WO2012051478A3 WO2012051478A3 (en) 2012-06-14

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JP (1) JP2013539952A (enExample)
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US10868557B2 (en) * 2018-03-30 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd Analog to digital converter with current steering stage
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Also Published As

Publication number Publication date
US20120092199A1 (en) 2012-04-19
US8269661B2 (en) 2012-09-18
WO2012051478A3 (en) 2012-06-14
CN103155416A (zh) 2013-06-12
JP2013539952A (ja) 2013-10-28
CN103155416B (zh) 2016-03-30

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