JP2013524552A - ハーフエッチングされた金属リードフレーム上に組み立てられたチップを有するボールグリッドアレイデバイス - Google Patents

ハーフエッチングされた金属リードフレーム上に組み立てられたチップを有するボールグリッドアレイデバイス Download PDF

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Publication number
JP2013524552A
JP2013524552A JP2013505049A JP2013505049A JP2013524552A JP 2013524552 A JP2013524552 A JP 2013524552A JP 2013505049 A JP2013505049 A JP 2013505049A JP 2013505049 A JP2013505049 A JP 2013505049A JP 2013524552 A JP2013524552 A JP 2013524552A
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JP
Japan
Prior art keywords
lead
lead frame
terminal
terminals
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2013505049A
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English (en)
Japanese (ja)
Other versions
JP2013524552A5 (enExample
Inventor
シー ハビエル レイナルド
ケイ コドゥリ スリーニーバサン
Original Assignee
日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本テキサス・インスツルメンツ株式会社, テキサス インスツルメンツ インコーポレイテッド filed Critical 日本テキサス・インスツルメンツ株式会社
Publication of JP2013524552A publication Critical patent/JP2013524552A/ja
Publication of JP2013524552A5 publication Critical patent/JP2013524552A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H10W70/415—Leadframe inner leads serving as die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/042—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/456—Materials
    • H10W70/457—Materials of metallic layers on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5366—Shapes of wire connectors the bond wires having kinks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP2013505049A 2010-04-12 2011-04-12 ハーフエッチングされた金属リードフレーム上に組み立てられたチップを有するボールグリッドアレイデバイス Pending JP2013524552A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US32308810P 2010-04-12 2010-04-12
US61/323,088 2010-04-12
US12/902,306 2010-10-12
US12/902,306 US20110248392A1 (en) 2010-04-12 2010-10-12 Ball-Grid Array Device Having Chip Assembled on Half-Etched metal Leadframe
PCT/US2011/032094 WO2011130252A2 (en) 2010-04-12 2011-04-12 Ball-grid array device having chip assembled on half-etched metal leadframe

Publications (2)

Publication Number Publication Date
JP2013524552A true JP2013524552A (ja) 2013-06-17
JP2013524552A5 JP2013524552A5 (enExample) 2014-05-29

Family

ID=44760335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013505049A Pending JP2013524552A (ja) 2010-04-12 2011-04-12 ハーフエッチングされた金属リードフレーム上に組み立てられたチップを有するボールグリッドアレイデバイス

Country Status (4)

Country Link
US (1) US20110248392A1 (enExample)
JP (1) JP2013524552A (enExample)
CN (1) CN102844860A (enExample)
WO (1) WO2011130252A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112022002753T5 (de) 2021-05-24 2024-03-07 Aoi Electronics Co., Ltd. Halbleiterbauelement und verfahren zur herstellung desselben

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CN102879246A (zh) * 2012-09-28 2013-01-16 无锡江南计算技术研究所 封装芯片金相制样方法以及金相样品模具
US8710636B1 (en) * 2013-02-04 2014-04-29 Freescale Semiconductor, Inc. Lead frame array package with flip chip die attach
US9190606B2 (en) * 2013-03-15 2015-11-17 Allegro Micosystems, LLC Packaging for an electronic device
US10345343B2 (en) 2013-03-15 2019-07-09 Allegro Microsystems, Llc Current sensor isolation
CN104465593B (zh) * 2014-11-13 2018-10-19 苏州日月新半导体有限公司 半导体封装体及封装方法
US9640468B2 (en) * 2014-12-24 2017-05-02 Stmicroelectronics S.R.L. Process for manufacturing a package for a surface-mount semiconductor device and semiconductor device
CN105720035A (zh) * 2016-03-25 2016-06-29 上海凯虹科技电子有限公司 引线框架及采用该引线框架的封装体
US11081429B2 (en) * 2019-10-14 2021-08-03 Texas Instruments Incorporated Finger pad leadframe
JP2022140870A (ja) * 2021-03-15 2022-09-29 株式会社村田製作所 回路モジュール
US11768230B1 (en) 2022-03-30 2023-09-26 Allegro Microsystems, Llc Current sensor integrated circuit with a dual gauge lead frame

Citations (6)

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JPH1174404A (ja) * 1997-08-28 1999-03-16 Nec Corp ボールグリッドアレイ型半導体装置
JPH11233683A (ja) * 1998-02-10 1999-08-27 Dainippon Printing Co Ltd 樹脂封止型半導体装置とそれに用いられる回路部材および樹脂封止型半導体装置の製造方法
JP2004031650A (ja) * 2002-06-26 2004-01-29 Sony Corp リードレスパッケージおよび半導体装置
JP2005116687A (ja) * 2003-10-06 2005-04-28 Renesas Technology Corp リードフレーム、半導体装置及び半導体装置の製造方法
JP2007243220A (ja) * 2007-05-14 2007-09-20 Renesas Technology Corp 樹脂封止型半導体パッケージ
JP2009164594A (ja) * 2007-12-11 2009-07-23 Dainippon Printing Co Ltd 半導体装置用基板、樹脂封止型半導体装置、半導体装置用基板の製造方法および樹脂封止型半導体装置の製造方法

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US6025640A (en) * 1997-07-16 2000-02-15 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device
US6281568B1 (en) * 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
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US7608482B1 (en) * 2006-12-21 2009-10-27 National Semiconductor Corporation Integrated circuit package with molded insulation
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JP2011517069A (ja) * 2009-03-06 2011-05-26 カイシン インコーポレイテッド 高密度コンタクトを有するリードレス集積回路パッケージ

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Publication number Priority date Publication date Assignee Title
JPH1174404A (ja) * 1997-08-28 1999-03-16 Nec Corp ボールグリッドアレイ型半導体装置
JPH11233683A (ja) * 1998-02-10 1999-08-27 Dainippon Printing Co Ltd 樹脂封止型半導体装置とそれに用いられる回路部材および樹脂封止型半導体装置の製造方法
JP2004031650A (ja) * 2002-06-26 2004-01-29 Sony Corp リードレスパッケージおよび半導体装置
JP2005116687A (ja) * 2003-10-06 2005-04-28 Renesas Technology Corp リードフレーム、半導体装置及び半導体装置の製造方法
JP2007243220A (ja) * 2007-05-14 2007-09-20 Renesas Technology Corp 樹脂封止型半導体パッケージ
JP2009164594A (ja) * 2007-12-11 2009-07-23 Dainippon Printing Co Ltd 半導体装置用基板、樹脂封止型半導体装置、半導体装置用基板の製造方法および樹脂封止型半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112022002753T5 (de) 2021-05-24 2024-03-07 Aoi Electronics Co., Ltd. Halbleiterbauelement und verfahren zur herstellung desselben
US12660658B2 (en) 2021-05-24 2026-06-16 Aoi Electronics Co., Ltd. Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
WO2011130252A2 (en) 2011-10-20
US20110248392A1 (en) 2011-10-13
CN102844860A (zh) 2012-12-26
WO2011130252A3 (en) 2012-01-26

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