JP2013522917A - コアレスパッケージを備えた電磁干渉シールド用の金属充填ダイバックサイドフィルムの形成方法 - Google Patents
コアレスパッケージを備えた電磁干渉シールド用の金属充填ダイバックサイドフィルムの形成方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000002184 metal Substances 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 14
- 239000012876 carrier material Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000003989 dielectric material Substances 0.000 claims abstract description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 239000000945 filler Substances 0.000 claims description 8
- 239000002245 particle Substances 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 239000002923 metal particle Substances 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims description 2
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- 238000000151 deposition Methods 0.000 claims 1
- 238000004377 microelectronic Methods 0.000 abstract description 9
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- 238000004806 packaging method and process Methods 0.000 abstract description 4
- 230000008569 process Effects 0.000 description 9
- 238000004891 communication Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 239000004593 Epoxy Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Abstract
Description
Claims (30)
- 方法は:
キャリア材料の中に空洞を形成するステップであって、前記キャリア材料は、エッチストップ層によって分離される上層と下層とを含む、ステップと;
前記空洞内にダイを付着するステップであって、前記ダイのバックサイドはDBFを含む、ステップと;
前記ダイに近接した前記キャリア材料の下層上にPoPランドを形成するステップと;
前記ダイに近接して前記キャリア材料の下層上に誘電材料を形成するステップと;
前記誘電材料上に層をビルドアップすることにより、コアレス基板を形成するステップと;
前記キャリア材料の上層と下層及びエッチストップ層を前記コアレス基板から除去するステップとを含む、方法。 - 前記DBFは前記ダイ上に留まる、請求項1記載の方法
- 前記DBFはEMIシールドを含む、請求項1記載の方法。
- 前記DBFは接着剤を含み、該接着剤は前記キャリア材料の下層に付着する、請求項1記載の方法。
- 前記キャリア材料とエッチストップ層を、それらが前記コアレス基板上に配置される間に、除去するステップを含む、請求項1記載の方法。
- 前記DBFは金属充填剤を含む、請求項1記載の方法。
- 前記金属充填剤は、銅と銀のうち少なくとも1つを含み、粒子サイズは約10ミクロンを下回る、請求項6記載の方法。
- 前記コアレス基板はコアレスなバンプレスビルドアップ層パッケージの一部を含む、請求項1記載の方法。
- 方法は:
キャリア材料の中に空洞を形成するステップと;
前記空洞内にダイを付着するステップであって、前記ダイのバックサイドは金属充填DBFを含む、ステップと;
前記ダイに近接した前記キャリア材料の下層上にPoPランド構造を形成するステップと;
前記ダイに近接して前記キャリア材料の底面側に誘電材料を形成するステップと;
前記誘電材料上に層をビルドアップすることによりコアレス基板を形成するステップであって、ビアが形成されてPoPランド構造と接続する、ステップと;
前記キャリア材料を前記コアレス基板から除去するステップと、を含む方法。 - 前記キャリア材料はエッチストップ層によって分離される上層と下層とを含む、請求項9記載の方法。
- 前記DBFは前記コアレス基板に付着されて残る、請求項9記載の方法。
- 前記コアレス基板は、コアレスなバンプレスビルドアップ層パッケージの一部を含む、請求項9記載の方法。
- 前記PoPランド構造のトップ面は、前記コアレスなバンプレスビルドアップ層パッケージのトップ面と同一平面である、請求項10記載の方法。
- 構造は:
コアレス基板の中に埋め込まれたダイと;
前記ダイに近接する誘電材料と;
前記ダイのダイパッドエリアに配置されたダイパッド相互接続構造と;
前記ダイのバックサイド上に配置されたDBFと、を含む構造。 - 前記DBFはEMIシールドを含む、請求項14記載の構造。
- 前記コアレス基板は、コアレスなバンプレスビルドアップパッケージ構造の一部を含む、請求項14記載の構造。
- 前記DBFは接着剤を含む、請求項14記載の構造。
- 前記DBFは金属充填粒子を含む、請求項14記載の構造。
- 金属充填粒子は、銅と銀のうち少なくとも1つを含む、請求項18記載の構造。
- 前記金属充填粒子は、約10ミクロンより小さい粒子サイズを有し、ダイは、機能化キャリア構造のトップ面と同一平面であり、前記ダイは前記コアレス基板の中に埋め込まれている、請求項18記載の構造。
- 構造は:
コアレス基板の中に埋め込まれているダイであって、DBFが前記ダイのバックサイド上に配置される、ダイと;
前記ダイに近接する誘電材料と;
前記ダイのダイパッド領域に配置されたダイパッド相互接続構造と;
非ダイ領域内に配置された前記コアレス基板内のビアであって、前記ビアはPoPランドに接続され、前記PoPランドは、前記ダイに近接する前記コアレス基板の範囲内に配置され、前記PoPランドのトップ面は前記コアレス基板のトップ面と同一平面である、ビアと、を有する、構造。 - 前記DBFはEMIシールドを含む、請求項21記載の構造。
- 前記コアレス基板は、コアレスなバンプレスビルドアップパッケージ構造の一部を含む、請求項21記載の構造。
- 前記DBFは金属粒子を含む、請求項21記載の構造。
- 前記ダイは前記コアレスなバンプレスビルドアップパッケージの中に完全に埋め込まれている、請求項23記載の構造。
- 前記DBFの一部は前記コアレスなバンプレスビルドアップパッケージの中に埋め込まれている、請求項25記載の構造。
- 前記コアレスなバンプレスビルドアップパッケージはRFコンポーネントを含む、請求項24記載の構造。
- 前記構造に通信可能に接続されるバスと;
前記バスに通信可能に接続されるDRAMとを有するシステムを含む、請求項21記載の構造。 - 前記ダイは、前記コアレスなバンプレスビルドアップパッケージのフィレット部分のトップ面と同一平面である、請求項23記載の構造。
- 前記DBFはグラス・クロスのバックボーンを含む、請求項21記載の構造。
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PCT/US2011/031079 WO2011126973A2 (en) | 2010-04-06 | 2011-04-04 | Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014063950A (ja) * | 2012-09-24 | 2014-04-10 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8742561B2 (en) | 2009-12-29 | 2014-06-03 | Intel Corporation | Recessed and embedded die coreless package |
US8901724B2 (en) | 2009-12-29 | 2014-12-02 | Intel Corporation | Semiconductor package with embedded die and its methods of fabrication |
US8535989B2 (en) | 2010-04-02 | 2013-09-17 | Intel Corporation | Embedded semiconductive chips in reconstituted wafers, and systems containing same |
US8319318B2 (en) | 2010-04-06 | 2012-11-27 | Intel Corporation | Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages |
US8431438B2 (en) | 2010-04-06 | 2013-04-30 | Intel Corporation | Forming in-situ micro-feature structures with coreless packages |
US8618652B2 (en) * | 2010-04-16 | 2013-12-31 | Intel Corporation | Forming functionalized carrier structures with coreless packages |
US8939347B2 (en) | 2010-04-28 | 2015-01-27 | Intel Corporation | Magnetic intermetallic compound interconnect |
US9847308B2 (en) | 2010-04-28 | 2017-12-19 | Intel Corporation | Magnetic intermetallic compound interconnect |
US8313958B2 (en) | 2010-05-12 | 2012-11-20 | Intel Corporation | Magnetic microelectronic device attachment |
US8434668B2 (en) | 2010-05-12 | 2013-05-07 | Intel Corporation | Magnetic attachment structure |
US8609532B2 (en) | 2010-05-26 | 2013-12-17 | Intel Corporation | Magnetically sintered conductive via |
US20120001339A1 (en) | 2010-06-30 | 2012-01-05 | Pramod Malatkar | Bumpless build-up layer package design with an interposer |
US8372666B2 (en) | 2010-07-06 | 2013-02-12 | Intel Corporation | Misalignment correction for embedded microelectronic die applications |
US8623699B2 (en) * | 2010-07-26 | 2014-01-07 | General Electric Company | Method of chip package build-up |
US8754516B2 (en) | 2010-08-26 | 2014-06-17 | Intel Corporation | Bumpless build-up layer package with pre-stacked microelectronic devices |
US8304913B2 (en) | 2010-09-24 | 2012-11-06 | Intel Corporation | Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby |
TWI538071B (zh) * | 2010-11-16 | 2016-06-11 | 星科金朋有限公司 | 具連接結構之積體電路封裝系統及其製造方法 |
JP2012146963A (ja) * | 2010-12-20 | 2012-08-02 | Shinko Electric Ind Co Ltd | 半導体パッケージの製造方法及び半導体パッケージ |
US8421245B2 (en) | 2010-12-22 | 2013-04-16 | Intel Corporation | Substrate with embedded stacked through-silicon via die |
US8937382B2 (en) | 2011-06-27 | 2015-01-20 | Intel Corporation | Secondary device integration into coreless microelectronic device packages |
US8848380B2 (en) * | 2011-06-30 | 2014-09-30 | Intel Corporation | Bumpless build-up layer package warpage reduction |
DE112011105848B4 (de) * | 2011-11-14 | 2021-02-18 | Intel Corporation | Verfahren für das Bumping einer Chip-Rückseite |
US9224674B2 (en) * | 2011-12-15 | 2015-12-29 | Intel Corporation | Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages |
US9299602B2 (en) * | 2011-12-20 | 2016-03-29 | Intel Corporation | Enabling package-on-package (PoP) pad surface finishes on bumpless build-up layer (BBUL) package |
WO2013095363A1 (en) * | 2011-12-20 | 2013-06-27 | Intel Corporation | Microelectronic package and stacked microelectronic assembly and computing system containing same |
US8901755B2 (en) * | 2012-03-20 | 2014-12-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive layer over metal substrate for electrical interconnect of semiconductor die |
US9257368B2 (en) | 2012-05-14 | 2016-02-09 | Intel Corporation | Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias |
DE112012006469B4 (de) | 2012-06-08 | 2022-05-05 | Intel Corporation | Mikroelektronisches Gehäuse mit nicht komplanaren gekapselten mikroelektronischen Bauelementen und einer Aufbauschicht ohne Kontaktierhügel |
US20140175657A1 (en) * | 2012-12-21 | 2014-06-26 | Mihir A. Oka | Methods to improve laser mark contrast on die backside film in embedded die packages |
US9530718B2 (en) | 2012-12-26 | 2016-12-27 | Intel Corporation | DBF film as a thermal interface material |
CN104299919B (zh) * | 2013-07-15 | 2017-05-24 | 碁鼎科技秦皇岛有限公司 | 无芯层封装结构及其制造方法 |
KR102192356B1 (ko) | 2013-07-29 | 2020-12-18 | 삼성전자주식회사 | 반도체 패키지 |
US9653438B2 (en) | 2014-08-21 | 2017-05-16 | General Electric Company | Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof |
KR102314774B1 (ko) | 2014-11-26 | 2021-10-21 | 삼성전자주식회사 | 반도체 패키지 |
WO2016187748A1 (en) * | 2015-05-22 | 2016-12-01 | 3M Innovative Properties Company | Viscoelastic electromagnetic interference (emi), shock and vibration absorber and methods of making the same |
US9985010B2 (en) * | 2015-05-22 | 2018-05-29 | Qualcomm Incorporated | System, apparatus, and method for embedding a device in a faceup workpiece |
US9811627B2 (en) * | 2015-12-08 | 2017-11-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of component partitions on system on chip and device thereof |
KR102497577B1 (ko) | 2015-12-18 | 2023-02-10 | 삼성전자주식회사 | 반도체 패키지의 제조방법 |
CN107295746B (zh) * | 2016-03-31 | 2021-06-15 | 奥特斯(中国)有限公司 | 器件载体及其制造方法 |
CN108701680B (zh) * | 2016-03-31 | 2023-05-30 | 英特尔公司 | 带有使用金属层和通孔的电磁干扰屏蔽的半导体封装 |
US10541153B2 (en) | 2017-08-03 | 2020-01-21 | General Electric Company | Electronics package with integrated interconnect structure and method of manufacturing thereof |
US10541209B2 (en) * | 2017-08-03 | 2020-01-21 | General Electric Company | Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof |
US10804115B2 (en) | 2017-08-03 | 2020-10-13 | General Electric Company | Electronics package with integrated interconnect structure and method of manufacturing thereof |
KR102504293B1 (ko) | 2017-11-29 | 2023-02-27 | 삼성전자 주식회사 | 패키지 온 패키지 형태의 반도체 패키지 |
US11398445B2 (en) | 2020-05-29 | 2022-07-26 | General Electric Company | Mechanical punched via formation in electronics package and electronics package formed thereby |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01258458A (ja) * | 1988-04-08 | 1989-10-16 | Nec Corp | ウェーハ集積型集積回路 |
JPH04261029A (ja) * | 1991-02-13 | 1992-09-17 | Hitachi Ltd | ペレット付け方法 |
JP2004140325A (ja) * | 2002-08-23 | 2004-05-13 | Shinko Electric Ind Co Ltd | 半導体パッケージ及び半導体装置 |
JP2004537861A (ja) * | 2001-08-01 | 2004-12-16 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 電子部品パッケージ用emi遮蔽 |
JP2005209689A (ja) * | 2004-01-20 | 2005-08-04 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2006032379A (ja) * | 2004-07-12 | 2006-02-02 | Akita Denshi Systems:Kk | 積層半導体装置及びその製造方法 |
JP2006066612A (ja) * | 2004-08-26 | 2006-03-09 | Seiko Epson Corp | フリップ実装した高周波モジュール |
WO2006046713A1 (ja) * | 2004-10-28 | 2006-05-04 | Kyocera Corporation | 電子部品モジュール及び無線通信機器 |
JP2006222400A (ja) * | 2005-02-14 | 2006-08-24 | Sumitomo Bakelite Co Ltd | 接着剤、半導体装置及び半導体装置の製造方法 |
JP2008010705A (ja) * | 2006-06-30 | 2008-01-17 | Phoenix Precision Technology Corp | チップ埋め込み基板のパッケージ構造 |
WO2009001564A1 (ja) * | 2007-06-28 | 2008-12-31 | Panasonic Corporation | 半導体素子の実装構造体及びその製造方法、半導体素子の実装方法、並びに加圧ツール |
JP2009158744A (ja) * | 2007-12-27 | 2009-07-16 | Shinko Electric Ind Co Ltd | 電子装置及びその製造方法及び配線基板及びその製造方法 |
JP2009194322A (ja) * | 2008-02-18 | 2009-08-27 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法、半導体装置及び配線基板 |
Family Cites Families (85)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5355102A (en) * | 1990-04-05 | 1994-10-11 | General Electric Company | HDI impedance matched microwave circuit assembly |
US5151769A (en) * | 1991-04-04 | 1992-09-29 | General Electric Company | Optically patterned RF shield for an integrated circuit chip for analog and/or digital operation at microwave frequencies |
US5353498A (en) | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US5527741A (en) | 1994-10-11 | 1996-06-18 | Martin Marietta Corporation | Fabrication and structures of circuit modules with flexible interconnect layers |
US5841193A (en) | 1996-05-20 | 1998-11-24 | Epic Technologies, Inc. | Single chip modules, repairable multichip modules, and methods of fabrication thereof |
TWI255853B (en) | 1998-08-21 | 2006-06-01 | Kirin Brewery | Method for modifying chromosomes |
US6306680B1 (en) | 1999-02-22 | 2001-10-23 | General Electric Company | Power overlay chip scale packages for discrete power devices |
US6239482B1 (en) | 1999-06-21 | 2001-05-29 | General Electric Company | Integrated circuit package including window frame |
US6242282B1 (en) | 1999-10-04 | 2001-06-05 | General Electric Company | Circuit chip package and fabrication method |
US6271469B1 (en) | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
US6154366A (en) | 1999-11-23 | 2000-11-28 | Intel Corporation | Structures and processes for fabricating moisture resistant chip-on-flex packages |
US6426545B1 (en) | 2000-02-10 | 2002-07-30 | Epic Technologies, Inc. | Integrated circuit structures and methods employing a low modulus high elongation photodielectric |
US6396148B1 (en) | 2000-02-10 | 2002-05-28 | Epic Technologies, Inc. | Electroless metal connection structures and methods |
US6555908B1 (en) | 2000-02-10 | 2003-04-29 | Epic Technologies, Inc. | Compliant, solderable input/output bump structures |
US6586836B1 (en) | 2000-03-01 | 2003-07-01 | Intel Corporation | Process for forming microelectronic packages and intermediate structures formed therewith |
US6734534B1 (en) | 2000-08-16 | 2004-05-11 | Intel Corporation | Microelectronic substrate with integrated devices |
US20020020898A1 (en) | 2000-08-16 | 2002-02-21 | Vu Quat T. | Microelectronic substrates with integrated devices |
US6586822B1 (en) | 2000-09-08 | 2003-07-01 | Intel Corporation | Integrated core microelectronic package |
US6713859B1 (en) | 2000-09-13 | 2004-03-30 | Intel Corporation | Direct build-up layer on an encapsulated die package having a moisture barrier structure |
US6489185B1 (en) | 2000-09-13 | 2002-12-03 | Intel Corporation | Protective film for the fabrication of direct build-up layers on an encapsulated die package |
US6617682B1 (en) | 2000-09-28 | 2003-09-09 | Intel Corporation | Structure for reducing die corner and edge stresses in microelectronic packages |
US6709898B1 (en) | 2000-10-04 | 2004-03-23 | Intel Corporation | Die-in-heat spreader microelectronic package |
US6423570B1 (en) | 2000-10-18 | 2002-07-23 | Intel Corporation | Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby |
US6555906B2 (en) | 2000-12-15 | 2003-04-29 | Intel Corporation | Microelectronic package having a bumpless laminated interconnection layer |
US6703400B2 (en) | 2001-02-23 | 2004-03-09 | Schering Corporation | Methods for treating multidrug resistance |
US6706553B2 (en) | 2001-03-26 | 2004-03-16 | Intel Corporation | Dispensing process for fabrication of microelectronic packages |
US6894399B2 (en) | 2001-04-30 | 2005-05-17 | Intel Corporation | Microelectronic device having signal distribution functionality on an interfacial layer thereof |
US6888240B2 (en) | 2001-04-30 | 2005-05-03 | Intel Corporation | High performance, low cost microelectronic circuit package with interposer |
US7071024B2 (en) | 2001-05-21 | 2006-07-04 | Intel Corporation | Method for packaging a microelectronic device using on-die bond pad expansion |
US6586276B2 (en) | 2001-07-11 | 2003-07-01 | Intel Corporation | Method for fabricating a microelectronic device using wafer-level adhesion layer deposition |
US7183658B2 (en) | 2001-09-05 | 2007-02-27 | Intel Corporation | Low cost microelectronic circuit package |
US6580611B1 (en) | 2001-12-21 | 2003-06-17 | Intel Corporation | Dual-sided heat removal system |
US6841413B2 (en) | 2002-01-07 | 2005-01-11 | Intel Corporation | Thinned die integrated circuit package |
JP3923368B2 (ja) * | 2002-05-22 | 2007-05-30 | シャープ株式会社 | 半導体素子の製造方法 |
TWI246761B (en) | 2003-05-14 | 2006-01-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with build-up layers formed on chip and fabrication method of the semiconductor package |
TWM249376U (en) * | 2003-11-06 | 2004-11-01 | Chipmos Technologies Inc | Image sensor with low noise |
JP2006059863A (ja) | 2004-08-17 | 2006-03-02 | Cmk Corp | パッケージ基板及びその製造方法 |
TWI240390B (en) | 2004-12-09 | 2005-09-21 | Phoenix Prec Technology Corp | Semiconductor package structure and method for fabricating the same |
US7442581B2 (en) | 2004-12-10 | 2008-10-28 | Freescale Semiconductor, Inc. | Flexible carrier and release method for high volume electronic package fabrication |
JP4602208B2 (ja) | 2004-12-15 | 2010-12-22 | 新光電気工業株式会社 | 電子部品実装構造体及びその製造方法 |
US7109055B2 (en) | 2005-01-20 | 2006-09-19 | Freescale Semiconductor, Inc. | Methods and apparatus having wafer level chip scale package for sensing elements |
TWI269423B (en) | 2005-02-02 | 2006-12-21 | Phoenix Prec Technology Corp | Substrate assembly with direct electrical connection as a semiconductor package |
US7160755B2 (en) | 2005-04-18 | 2007-01-09 | Freescale Semiconductor, Inc. | Method of forming a substrateless semiconductor package |
US7262444B2 (en) * | 2005-08-17 | 2007-08-28 | General Electric Company | Power semiconductor packaging method and structure |
JP4452222B2 (ja) * | 2005-09-07 | 2010-04-21 | 新光電気工業株式会社 | 多層配線基板及びその製造方法 |
US7425464B2 (en) | 2006-03-10 | 2008-09-16 | Freescale Semiconductor, Inc. | Semiconductor device packaging |
US8293584B2 (en) * | 2006-08-04 | 2012-10-23 | Stats Chippac Ltd. | Integrated circuit package system with filled wafer recess |
US7723164B2 (en) | 2006-09-01 | 2010-05-25 | Intel Corporation | Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same |
US7659143B2 (en) | 2006-09-29 | 2010-02-09 | Intel Corporation | Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same |
US7476563B2 (en) | 2006-11-17 | 2009-01-13 | Freescale Semiconductor, Inc. | Method of packaging a device using a dielectric layer |
US7588951B2 (en) | 2006-11-17 | 2009-09-15 | Freescale Semiconductor, Inc. | Method of packaging a semiconductor device and a prefabricated connector |
US7632715B2 (en) | 2007-01-05 | 2009-12-15 | Freescale Semiconductor, Inc. | Method of packaging semiconductor devices |
US20080192776A1 (en) | 2007-02-09 | 2008-08-14 | Fleming Kristoffer D | Mechanism for increasing UWB MAC efficiency and bandwidth via the period inclusion of PHY preambles for synchronization |
DE102007020656B4 (de) * | 2007-04-30 | 2009-05-07 | Infineon Technologies Ag | Werkstück mit Halbleiterchips, Halbleiterbauteil und Verfahren zur Herstellung eines Werkstücks mit Halbleiterchips |
US8039309B2 (en) * | 2007-05-10 | 2011-10-18 | Texas Instruments Incorporated | Systems and methods for post-circuitization assembly |
US7648858B2 (en) | 2007-06-19 | 2010-01-19 | Freescale Semiconductor, Inc. | Methods and apparatus for EMI shielding in multi-chip modules |
US8384199B2 (en) | 2007-06-25 | 2013-02-26 | Epic Technologies, Inc. | Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system |
US7595226B2 (en) | 2007-08-29 | 2009-09-29 | Freescale Semiconductor, Inc. | Method of packaging an integrated circuit die |
US7651889B2 (en) | 2007-09-13 | 2010-01-26 | Freescale Semiconductor, Inc. | Electromagnetic shield formation for integrated circuit die package |
US20090072382A1 (en) | 2007-09-18 | 2009-03-19 | Guzek John S | Microelectronic package and method of forming same |
US9941245B2 (en) | 2007-09-25 | 2018-04-10 | Intel Corporation | Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate |
US20090079064A1 (en) | 2007-09-25 | 2009-03-26 | Jiamiao Tang | Methods of forming a thin tim coreless high density bump-less package and structures formed thereby |
US7851905B2 (en) | 2007-09-26 | 2010-12-14 | Intel Corporation | Microelectronic package and method of cooling an interconnect feature in same |
US8035216B2 (en) | 2008-02-22 | 2011-10-11 | Intel Corporation | Integrated circuit package and method of manufacturing same |
US8058723B2 (en) * | 2008-03-19 | 2011-11-15 | Phoenix Precision Technology Corporation | Package structure in which coreless substrate has direct electrical connections to semiconductor chip and manufacturing method thereof |
US7976708B2 (en) * | 2008-05-12 | 2011-07-12 | Secretary, Department of Atormic Energy | Innovative cut-and-feed operation for enhancing the performance of ion-exchange chromatographic separation |
US8093704B2 (en) | 2008-06-03 | 2012-01-10 | Intel Corporation | Package on package using a bump-less build up layer (BBUL) package |
US8097489B2 (en) * | 2009-03-23 | 2012-01-17 | Stats Chippac, Ltd. | Semiconductor device and method of mounting pre-fabricated shielding frame over semiconductor die |
US20110108999A1 (en) | 2009-11-06 | 2011-05-12 | Nalla Ravi K | Microelectronic package and method of manufacturing same |
US8901724B2 (en) | 2009-12-29 | 2014-12-02 | Intel Corporation | Semiconductor package with embedded die and its methods of fabrication |
US8742561B2 (en) | 2009-12-29 | 2014-06-03 | Intel Corporation | Recessed and embedded die coreless package |
US8891246B2 (en) | 2010-03-17 | 2014-11-18 | Intel Corporation | System-in-package using embedded-die coreless substrates, and processes of forming same |
US8535989B2 (en) | 2010-04-02 | 2013-09-17 | Intel Corporation | Embedded semiconductive chips in reconstituted wafers, and systems containing same |
US8319318B2 (en) | 2010-04-06 | 2012-11-27 | Intel Corporation | Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages |
US8431438B2 (en) | 2010-04-06 | 2013-04-30 | Intel Corporation | Forming in-situ micro-feature structures with coreless packages |
US8618652B2 (en) | 2010-04-16 | 2013-12-31 | Intel Corporation | Forming functionalized carrier structures with coreless packages |
US8313958B2 (en) | 2010-05-12 | 2012-11-20 | Intel Corporation | Magnetic microelectronic device attachment |
US20110316140A1 (en) | 2010-06-29 | 2011-12-29 | Nalla Ravi K | Microelectronic package and method of manufacturing same |
US20120001339A1 (en) | 2010-06-30 | 2012-01-05 | Pramod Malatkar | Bumpless build-up layer package design with an interposer |
US8372666B2 (en) | 2010-07-06 | 2013-02-12 | Intel Corporation | Misalignment correction for embedded microelectronic die applications |
US8304913B2 (en) | 2010-09-24 | 2012-11-06 | Intel Corporation | Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby |
US8786066B2 (en) | 2010-09-24 | 2014-07-22 | Intel Corporation | Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same |
US20120112336A1 (en) | 2010-11-05 | 2012-05-10 | Guzek John S | Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package |
US20120139095A1 (en) | 2010-12-03 | 2012-06-07 | Manusharow Mathew J | Low-profile microelectronic package, method of manufacturing same, and electronic assembly containing same |
US8508037B2 (en) | 2010-12-07 | 2013-08-13 | Intel Corporation | Bumpless build-up layer and laminated core hybrid structures and methods of assembling same |
-
2010
- 2010-04-06 US US12/755,201 patent/US8319318B2/en active Active
-
2011
- 2011-04-04 WO PCT/US2011/031079 patent/WO2011126973A2/en active Application Filing
- 2011-04-04 JP JP2013500250A patent/JP5599934B2/ja active Active
- 2011-04-04 KR KR1020127025222A patent/KR101409094B1/ko active IP Right Grant
- 2011-04-04 EP EP11766549.7A patent/EP2556534B1/en active Active
- 2011-04-04 CN CN201180017635.7A patent/CN102822963B/zh active Active
- 2011-04-06 TW TW100111819A patent/TWI521667B/zh active
-
2012
- 2012-10-25 US US13/660,095 patent/US8507324B2/en not_active Expired - Fee Related
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01258458A (ja) * | 1988-04-08 | 1989-10-16 | Nec Corp | ウェーハ集積型集積回路 |
JPH04261029A (ja) * | 1991-02-13 | 1992-09-17 | Hitachi Ltd | ペレット付け方法 |
JP2004537861A (ja) * | 2001-08-01 | 2004-12-16 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 電子部品パッケージ用emi遮蔽 |
JP2004140325A (ja) * | 2002-08-23 | 2004-05-13 | Shinko Electric Ind Co Ltd | 半導体パッケージ及び半導体装置 |
JP2005209689A (ja) * | 2004-01-20 | 2005-08-04 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2006032379A (ja) * | 2004-07-12 | 2006-02-02 | Akita Denshi Systems:Kk | 積層半導体装置及びその製造方法 |
JP2006066612A (ja) * | 2004-08-26 | 2006-03-09 | Seiko Epson Corp | フリップ実装した高周波モジュール |
WO2006046713A1 (ja) * | 2004-10-28 | 2006-05-04 | Kyocera Corporation | 電子部品モジュール及び無線通信機器 |
JP2006222400A (ja) * | 2005-02-14 | 2006-08-24 | Sumitomo Bakelite Co Ltd | 接着剤、半導体装置及び半導体装置の製造方法 |
JP2008010705A (ja) * | 2006-06-30 | 2008-01-17 | Phoenix Precision Technology Corp | チップ埋め込み基板のパッケージ構造 |
WO2009001564A1 (ja) * | 2007-06-28 | 2008-12-31 | Panasonic Corporation | 半導体素子の実装構造体及びその製造方法、半導体素子の実装方法、並びに加圧ツール |
JP2009158744A (ja) * | 2007-12-27 | 2009-07-16 | Shinko Electric Ind Co Ltd | 電子装置及びその製造方法及び配線基板及びその製造方法 |
JP2009194322A (ja) * | 2008-02-18 | 2009-08-27 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法、半導体装置及び配線基板 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014063950A (ja) * | 2012-09-24 | 2014-04-10 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
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EP2556534A4 (en) | 2013-11-27 |
EP2556534A2 (en) | 2013-02-13 |
US20130052776A1 (en) | 2013-02-28 |
WO2011126973A2 (en) | 2011-10-13 |
TW201203493A (en) | 2012-01-16 |
CN102822963B (zh) | 2016-08-10 |
WO2011126973A3 (en) | 2012-01-19 |
EP2556534B1 (en) | 2017-02-01 |
US20110241186A1 (en) | 2011-10-06 |
CN102822963A (zh) | 2012-12-12 |
KR20120132528A (ko) | 2012-12-05 |
KR101409094B1 (ko) | 2014-06-17 |
US8319318B2 (en) | 2012-11-27 |
US8507324B2 (en) | 2013-08-13 |
TWI521667B (zh) | 2016-02-11 |
JP5599934B2 (ja) | 2014-10-01 |
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