JP2013520101A - 広帯域アナログ無線周波数を処理する構成要素 - Google Patents
広帯域アナログ無線周波数を処理する構成要素 Download PDFInfo
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Abstract
【解決手段】積分器は、第1の電圧供給端子と第2の電圧供給端子との間に直列接続された、一対のpチャネルトランジスタ、一対の可変抵抗手段、および一対のnチャネルトランジスタを備える。pチャネルトランジスタのドレインが可変抵抗手段のドレインに電流を供給し、可変抵抗手段のソースがnチャネルトランジスタのドレインに電流を供給する。pチャネルトランジスタのゲートは、可変抵抗手段において反対側のトランジスタのドレインに対し、フィードフォワード形態で接続されてもよい。一対のnチャネルトランジスタのゲートに印加された相補的な入力信号によって駆動された積分器は、pチャネルトランジスタと可変抵抗手段との間のノードに相補的な出力を生成する。
【選択図】図4
Description
Claims (16)
- 広帯域アナログ無線周波数の積分器であって、
第1及び第2のpチャネルトランジスタであって、それぞれ、第1の電圧供給端子に並列に接続されたソース、およびドレインを有し、当該第1のpチャネルトランジスタの前記ドレインと、当該第2のpチャネルトランジスタの前記ドレインとが、互いに相補的な出力信号を提供する、第1及び第2のpチャネルトランジスタと、
第1及び第2の可変抵抗手段であって、
第1の可変抵抗手段は前記第1のpチャネルトランジスタのドレインに接続された第1端子および前記第2のpチャネルトランジスタのゲートに接続された第2端子を有し、
第2の可変抵抗手段は前記第2のpチャネルトランジスタのドレインに接続された第1端子および前記第1のpチャネルトランジスタのゲートに接続された第2端子を有する、第1及び第2の可変抵抗手段と、
第1及び第2のnチャネルトランジスタであって、
第1のnチャネルトランジスタは前記第1の可変抵抗手段の前記第2端子に接続されたドレイン、ゲート、および第2の電圧供給端子に電気的に導通したソースを有し、
第2のnチャネルトランジスタは前記第2の可変抵抗手段の前記第2端子に接続されたドレイン、ゲート、および第2の電圧供給端子に電気的に導通したソースを有し、
当該第1のnチャネルトランジスタの前記ゲートと、当該第2のnチャネルトランジスタの前記ゲートとが、互いに相補的な入力信号を受け取る、第1及び第2のnチャネルトランジスタとを備えた、広帯域アナログ無線周波数の積分器。 - 請求項1に記載の積分器において、さらに、
前記第2の電圧供給端子と前記第1及び第2のnチャネルトランジスタのソースとの間に直列接続されたバイアストランジスタを備えた、広帯域アナログ無線周波数の積分器。 - 請求項1に記載の積分器において、さらに、
前記第1及び第2のnチャネルトランジスタのゲートに電気的に導通して当該第1及び第2のnチャネルトランジスタの抵抗を制御する第3の電圧供給端子を備えた、広帯域アナログ無線周波数の積分器。 - 請求項1に記載の積分器において、ディープサブミクロン相補型金属酸化膜半導体技術、シリコンゲルマニウム技術、または絶縁体上シリコン技術を用いて作製された、広帯域アナログ無線周波数の積分器。
- 請求項1に記載の積分器において、前記トランジスタが、バイアスオフセットを減少させるように交互配置されている、広帯域アナログ無線周波数の積分器。
- 請求項1に記載の積分器において、さらに、
当該積分器の出力のサンプリングを調整するチューニング回路を備えた、広帯域アナログ無線周波数の積分器。 - 請求項6に記載の積分器において、前記チューニング回路が、DC較正回路とゲイン制御回路とを含む、広帯域アナログ無線周波数の積分器。
- 請求項1に記載の積分器において、
前記第1の可変抵抗手段が第3のnチャネルトランジスタを含み、
前記第2の可変抵抗手段が第4のnチャネルトランジスタを含み、
前記第3のnチャネルトランジスタは、前記第1のpチャネルトランジスタのドレインに接続されたドレイン、前記第2のpチャネルトランジスタのゲートに接続されたソース、およびゲートを有し、
前記第4のnチャネルトランジスタは、前記第2のpチャネルトランジスタのドレインに接続されたドレイン、前記第1のpチャネルトランジスタのゲートに接続されたソース、およびゲートを有し、
前記第3のnチャネルトランジスタのゲートと前記第4のnチャネルトランジスタのゲートとが互いに接続されている、広帯域アナログ無線周波数の積分器。 - 広帯域アナログ無線周波数の減衰器であって、
M個からなる複数の減衰器ブロックを備え、これらブロックは、それぞれ、
信号レールと出力ノードとの間に接続された第1のスイッチと、
オフセットレールと前記出力ノードとの間に接続された第2のスイッチと、
前記出力ノードと前記第1及び第2のスイッチとの間に直列接続された抵抗要素とを含み、
当該減衰器ブロックが、Nビットの精度であって、NがMよりも小さい、精度をもたらす、広帯域アナログ無線周波数の減衰器。 - 請求項9に記載の減衰器において、前記ブロックのうちの少なくとも1つにおける抵抗要素の抵抗値が、前記ブロックのうちの他の1つのブロックにおける抵抗値に対する素数に相当する、広帯域アナログ無線周波数の減衰器。
- 請求項9に記載の減衰器において、前記ブロックのそれぞれの前記抵抗要素の数値が、一様に分布したランダム変数によってディザリングされたものである、広帯域アナログ無線周波数の減衰器。
- 請求項9に記載の減衰器において、前記出力ノードで計測された誤差に基づいて前記第1及び第2のスイッチを制御するプログラム入力を設定することによって、較正が行われる、広帯域アナログ無線周波数の減衰器。
- 請求項9に記載の減衰器において、相補型金属酸化膜半導体技術、または絶縁体上シリコン技術を用いて作製された、広帯域アナログ無線周波数の減衰器。
- 広帯域アナログ無線周波数のスケーラブルな加算器であって、
出力ノードと接地レールとの間に並列接続された、N個からなる複数のスイッチと、
電源レールと前記出力ノードとの間に直列接続された抵抗要素とを備え、
前記スイッチのそれぞれが、それぞれ対応する電圧入力によって制御される、広帯域アナログ無線周波数のスケーラブルな加算器。 - 請求項14に記載の加算器において、前記Nが、加算すべき入力信号の数に基づいて決定される、広帯域アナログ無線周波数のスケーラブルな加算器。
- 請求項14に記載の加算器において、相補型金属酸化膜半導体技術、または絶縁体上シリコン技術を用いて作製された、広帯域アナログ無線周波数のスケーラブルな加算器。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US30406410P | 2010-02-12 | 2010-02-12 | |
US61/304,064 | 2010-02-12 | ||
US35910810P | 2010-06-28 | 2010-06-28 | |
US61/359,108 | 2010-06-28 | ||
PCT/US2011/024542 WO2011152896A1 (en) | 2010-02-12 | 2011-02-11 | Broadband analog radio-frequency components |
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KR20180042396A (ko) * | 2015-08-24 | 2018-04-25 | 자일링크스 인코포레이티드 | 송신기에서 변조 신호를 생성하기 위한 송신기 회로 및 방법 |
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WO2011152896A1 (en) | 2011-12-08 |
KR101310418B1 (ko) | 2013-09-24 |
EP2522073A1 (en) | 2012-11-14 |
EP2522073A4 (en) | 2014-06-11 |
CN102835027B (zh) | 2016-05-25 |
CN102835027A (zh) | 2012-12-19 |
US8866531B2 (en) | 2014-10-21 |
JP5870368B2 (ja) | 2016-03-01 |
KR20130001231A (ko) | 2013-01-03 |
US20120293233A1 (en) | 2012-11-22 |
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