JP2013214773A - 縦型の誘電体層を有する半導体素子構造 - Google Patents
縦型の誘電体層を有する半導体素子構造 Download PDFInfo
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Abstract
【解決手段】本発明の半導体素子は、第1面101、第2面102’、エッジ103、エッジ103に隣接するエッジ領域104を備える半導体ボディ100と、半導体ボディ100の垂直方向に伸びる第1誘電体層31によって互いに誘電的に絶縁されたドリフトゾーン11およびドリフト制御ゾーン21と、ドリフトゾーン11およびエッジ領域104に接触している、半導体ボディ100の第2面102’の領域にある第1接続ゾーン200と、ドリフトゾーン11と第1接続ゾーン200との間に配置された第3誘電体層43と、接続ゾーン24およびエッジ領域104の接続ゾーン71との間に接続された整流素子72とを含み、ドリフト制御ゾーン21は、少なくとも第2誘電体層32によってエッジ領域104から誘電的に絶縁されている。
【選択図】図15
Description
上述の各工程の間、例えばエピタキシー法の間に、誘電体層31の誘電特性が変化する、具体的には悪化することがある。従って、このような誘電体層31を、上述の工程の後または上記工程を行っている間に、例えばエッチング法によって除去し、改めて誘電体層31を形成することが都合がよい。
21’ 半導体区域
31 第1誘電体層
100 第1半導体ボディ
101 第1面
102’ 第2面
Claims (3)
- 第1面および第2面、エッジおよび上記エッジに水平方向において隣接するエッジ領域を備える半導体ボディと、
上記半導体ボディの垂直方向に伸びる第1誘電体層によって互いに誘電的に絶縁されたドリフトゾーンおよびドリフト制御ゾーンと、
上記ドリフトゾーンおよび上記エッジ領域に接触している、上記半導体ボディの第2面の領域にある第1接続ゾーンと、
上記ドリフト制御ゾーンおよび上記第1接続ゾーンの間に配置された第3誘電体層と、
上記第1面の領域内にある上記ドリフト制御ゾーンのコンタクトゾーン、および上記第1面の領域内にある上記エッジ領域のコンタクトゾーンの間に接続された整流素子とを含み、
上記ドリフト制御ゾーンは、少なくとも上記エッジ領域から第2誘電体層によって誘電的に絶縁されている、半導体素子。 - 上記ドリフト制御ゾーンは、第1ドープ区域、および、上記第1ドープ区域よりも高濃度にドープされた第2ドープ区域を有し、
上記第2ドープ区域は、上記第3誘電体層に沿って伸びている、請求項1に記載の半導体素子。 - 上記ドリフト制御ゾーンは、上記コンタクトゾーンおよび上記第2ドープ区域の間に配置された第3ドープ区域を有する、請求項2に記載の半導体素子。
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US12/241,828 US7943449B2 (en) | 2008-09-30 | 2008-09-30 | Semiconductor component structure with vertical dielectric layers |
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US7554137B2 (en) * | 2005-10-25 | 2009-06-30 | Infineon Technologies Austria Ag | Power semiconductor component with charge compensation structure and method for the fabrication thereof |
US7943449B2 (en) * | 2008-09-30 | 2011-05-17 | Infineon Technologies Austria Ag | Semiconductor component structure with vertical dielectric layers |
KR101481708B1 (ko) * | 2008-11-21 | 2015-01-12 | 삼성전자주식회사 | 리세스 채널 트랜지스터 및 이의 제조방법 |
US9396997B2 (en) | 2010-12-10 | 2016-07-19 | Infineon Technologies Ag | Method for producing a semiconductor component with insulated semiconductor mesas |
US9142665B2 (en) | 2010-12-10 | 2015-09-22 | Infineon Technologies Austria Ag | Semiconductor component with a semiconductor via |
US8541833B2 (en) | 2011-04-08 | 2013-09-24 | Infineon Technologies Austria Ag | Power transistor device vertical integration |
US9166028B2 (en) * | 2011-05-31 | 2015-10-20 | Infineon Technologies Austria Ag | Circuit configured to adjust the activation state of transistors based on load conditions |
US8604542B2 (en) * | 2011-08-23 | 2013-12-10 | Nan Ya Technology Corporation | Circuit structure with conductive and depletion regions to form tunable capacitors and resistors |
US20140063882A1 (en) * | 2012-08-30 | 2014-03-06 | Infineon Technologies Austria Ag | Circuit Arrangement with Two Transistor Devices |
FR3007576B1 (fr) * | 2013-06-19 | 2015-07-10 | Soitec Silicon On Insulator | Procede de transfert d'une couche de circuits. |
DE102013217300A1 (de) * | 2013-08-30 | 2014-05-08 | Robert Bosch Gmbh | MEMS-Bauelement mit einer mikromechanischen Mikrofonstruktur |
JP6448513B2 (ja) * | 2015-11-16 | 2019-01-09 | 株式会社東芝 | 半導体装置 |
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Also Published As
Publication number | Publication date |
---|---|
US20110101451A1 (en) | 2011-05-05 |
DE102009028485A1 (de) | 2010-04-22 |
JP2010087509A (ja) | 2010-04-15 |
JP5512208B2 (ja) | 2014-06-04 |
US20100078713A1 (en) | 2010-04-01 |
US8319261B2 (en) | 2012-11-27 |
DE102009028485B4 (de) | 2013-10-17 |
US7943449B2 (en) | 2011-05-17 |
JP5686860B2 (ja) | 2015-03-18 |
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