JP2013125905A - 配線パターンの形成方法及び半導体装置 - Google Patents
配線パターンの形成方法及び半導体装置 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000010410 layer Substances 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 28
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- 239000004020 conductor Substances 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 239000011229 interlayer Substances 0.000 claims abstract description 5
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- 239000002094 self assembled monolayer Substances 0.000 description 6
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- 125000005372 silanol group Chemical group 0.000 description 5
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- 125000003277 amino group Chemical group 0.000 description 4
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- 125000003396 thiol group Chemical group [H]S* 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 125000000524 functional group Chemical group 0.000 description 2
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- 239000010949 copper Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 125000002228 disulfide group Chemical group 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
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- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/31—Coating with metals
- C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
Abstract
【解決手段】本実施形態に係る配線パターンの形成方法は、基材の主面上に側面を有する絶縁パターンを形成する工程と、前記絶縁パターンの前記側面に、前記絶縁パターンの材料と親和性を有する自己組織化膜を形成する工程と、前記自己組織化膜の側面に導電性材料を析出させて導電層を形成する工程と、を備える。また、前記主面上において前記導電層の周囲を絶縁性の層間膜で覆う工程と、前記層間膜の表面に前記導電層を露出させる工程と、をさらに備える。
【選択図】図1
Description
また、配線パターンの形成方法として、無電解めっきにより導電層を析出させる方法もある。
このような配線パターンの形成においては、高精度に安定した形状を形成することが望まれる。
なお、図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比係数などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比係数が異なって表される場合もある。
また、本願明細書と各図において、既出の図に関して前述したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
図1は、第1の実施形態に係る配線パターンの形成方法を例示するフローチャートである。
すなわち、図1に表したように、本実施形態に係る配線パターンの形成方法は、絶縁パターンの形成(ステップS101)、自己組織化膜の形成(ステップS102)、導電層の形成(ステップS103)を備える。
絶縁層には、例えば酸化シリコンが用いられる。マスクパターンには、例えばフォトレジストが用いられる。
絶縁パターンが酸化シリコンを含む場合、自己組織化膜は、酸化シリコンにのみ吸着するシランカップリング剤を含む。
先ず、図2(a)に表したように、基板11の上に下地層12を形成する。基板11には、例えばシリコンが用いられる。なお、基板11は、シリコン以外の半導体基板やガラス等の絶縁性基板でもよい。また、基板11は、絶縁性基板に半導体層が形成されたものであってもよい。基板11には回路や素子が形成されているものも含まれる。
一例として、絶縁パターン21の幅は約20ナノメートル(nm)、隣り合う2つの絶縁パターン21の隙間は約20nmである。
一例として、スリミング後の絶縁パターン21の幅は約5nm、隣り合う2つの絶縁パターン21の隙間は約35nmである。
自己組織化膜30を形成するには、マスクパターンMPが残った絶縁パターン21を、自己組織化膜30の材料が含まれる溶媒に浸漬させる。
絶縁パターン21が酸化シリコンを含む場合、自己組織化膜30は酸化シリコンにのみ吸着するシランカップリング剤を含むものが好ましい。
一例として、自己組織化膜30及び触媒35を含む絶縁パターン21の幅は約10nm、隣り合う2つの絶縁パターン21の隙間は約30nmである。
一例として、導電層40の厚さ(配線パターンの幅)は約30nm、隣り合う2つの導電層40の隙間(隣り合う2つの配線パターンの隙間)は約10nmである。
一例として、絶縁部材50は、約1000nmの厚さで形成される。
また、第1の実施形態では、絶縁パターン21の側面21aに導電層40が形成されるため、絶縁パターン21によって導電層40が確実に支持される。したがって、細く、深い配線パターン1であっても、精度良く、安定して形成することができる。
一方、絶縁パターン21として誘電率の高い材料(例えば、HfSiO、Hf、Laなどの希土類金属、Hf、Al、Ta、Ti、La、Siなどの酸化物)を用いることにより、静電容量の大きなコンデンサが構成される。
次に、第2の実施形態に係る配線パターンの形成方法について説明する。
図5(a)〜図6(c)は、第2の実施形態に係る配線パターンの形成方法を例示する模式的断面図である。
先ず、図5(a)に表したように、絶縁パターン21を形成する。絶縁パターン21の形成は、先に説明した第1の実施形態と同様である(図2(a)〜(c)参照)。次に、絶縁パターン21の近傍の基材10に開口hを形成する。
開口hは、絶縁パターン21を形成した後に設けられても、絶縁パターン21を形成する前に設けられてもよい。
次に、第3の実施形態に係る半導体装置について説明する。
図7は、第3の実施形態に係る半導体装置を例示する模式的斜視図である。
図7に表したように、半導体装置110は、半導体素子100が設けられた基材10と、基材10の主面10aに設けられ、主面10a上に側面21aを有する絶縁パターン21と、絶縁パターン21の側面21aに設けられた自己組織化膜30と、自己組織化膜30の側面に設けられた導電層40と、を備える。導電層40には、導電層40の金属材料に対して還元力の高い材料(例えば、パラジウム)が含まれてもよい。
Claims (8)
- 基材の主面上に絶縁層を形成し、前記絶縁層の上にマスクパターンを形成し、前記マスクパターンを介して前記絶縁層をエッチングすることで、前記主面上に側面を有し前記マスクパターンの幅よりも細い幅の絶縁パターンを形成する工程と、
前記絶縁パターンの前記側面に、前記絶縁パターンの材料と親和性を有する自己組織化膜を形成する工程と、
前記自己組織化膜に触媒を付与し、前記触媒を介して導電性材料を析出させて導電層を形成する工程と、
を備えた配線パターンの形成方法。 - 基材の主面上に側面を有する絶縁パターンを形成する工程と、
前記絶縁パターンの前記側面に、前記絶縁パターンの材料と親和性を有する自己組織化膜を形成する工程と、
前記自己組織化膜の側面に導電性材料を析出させて導電層を形成する工程と、
を備えた配線パターンの形成方法。 - 前記絶縁パターンを形成する工程は、前記基材の前記主面上に絶縁層を形成し、前記絶縁層の上にマスクパターンを形成し、前記マスクパターンを介して前記絶縁層をエッチングすることを含む請求項2記載の配線パターンの形成方法。
- 前記絶縁パターンを形成する工程は、前記マスクパターンを介して前記絶縁層をエッチングしたのち、前記マスクパターンを残したまま前記絶縁パターンの幅を前記マスクパターンの幅よりも細くすることを含む請求項3記載の配線パターンの形成方法。
- 前記導電層を形成する工程は、前記自己組織化膜に触媒を付与し、前記触媒を介して前記導電性材料を析出させることを含む請求項2〜4のいずれか1つに記載の配線パターンの形成方法。
- 前記絶縁パターンは、酸化シリコンを含み、
前記自己組織化膜は、前記酸化シリコンにのみ吸着するシランカップリング剤を含む請求項2〜5のいずれか1つに記載の配線パターンの形成方法。 - 前記主面上において前記導電層の周囲を絶縁性の層間膜で覆う工程と、
前記層間膜の表面に前記導電層を露出させる工程と、
をさらに備えた請求項2〜6のいずれか1つに記載の配線パターンの形成方法。 - 半導体素子が設けられた基材と、
前記基材の主面に設けられ、前記主面上に側面を有する絶縁パターンと、
前記絶縁パターンの前記側面に設けられ、前記絶縁パターンの材料と親和性を有する自己組織化膜と、
前記自己組織化膜の側面に設けられた導電層と、
を備えた半導体装置。
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Application Number | Priority Date | Filing Date | Title |
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JP2011274772A JP5931428B2 (ja) | 2011-12-15 | 2011-12-15 | 配線パターンの形成方法及び半導体装置 |
US13/526,216 US8772164B2 (en) | 2011-12-15 | 2012-06-18 | Method for forming interconnection pattern and semiconductor device |
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JPH08107111A (ja) * | 1994-10-03 | 1996-04-23 | Toshiba Corp | 半導体装置の製造方法 |
JPH09321138A (ja) * | 1996-05-29 | 1997-12-12 | Nec Corp | 半導体装置の製造方法 |
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JP2005051151A (ja) | 2003-07-31 | 2005-02-24 | Seiko Epson Corp | 導電層の製造方法、導電層を有する基板、および電子デバイス |
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WO2009066263A1 (en) * | 2007-11-21 | 2009-05-28 | Eskom Holdings Ltd | Method of surface modification of metallic hydride forming materials |
JP2010171398A (ja) | 2008-12-26 | 2010-08-05 | Toshiba Corp | 半導体装置の製造方法 |
JP5404361B2 (ja) | 2009-12-11 | 2014-01-29 | 株式会社東芝 | 半導体基板の表面処理装置及び方法 |
JP5424848B2 (ja) | 2009-12-15 | 2014-02-26 | 株式会社東芝 | 半導体基板の表面処理装置及び方法 |
US9487600B2 (en) * | 2010-08-17 | 2016-11-08 | Uchicago Argonne, Llc | Ordered nanoscale domains by infiltration of block copolymers |
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JPH02189923A (ja) * | 1989-01-18 | 1990-07-25 | Nec Corp | 半導体集積回路装置の製造方法 |
JPH08107111A (ja) * | 1994-10-03 | 1996-04-23 | Toshiba Corp | 半導体装置の製造方法 |
JPH09321138A (ja) * | 1996-05-29 | 1997-12-12 | Nec Corp | 半導体装置の製造方法 |
JP2007096129A (ja) * | 2005-09-29 | 2007-04-12 | Kyoto Univ | 分子トランジスタおよびその製造方法、並びにそれを用いた不揮発性メモリおよび圧電センサ |
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JP2011194720A (ja) * | 2010-03-19 | 2011-10-06 | Waseda Univ | 金型製造方法およびその方法により形成された金型 |
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US20130154087A1 (en) | 2013-06-20 |
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