JP2013079941A5 - - Google Patents

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JP2013079941A5
JP2013079941A5 JP2012192370A JP2012192370A JP2013079941A5 JP 2013079941 A5 JP2013079941 A5 JP 2013079941A5 JP 2012192370 A JP2012192370 A JP 2012192370A JP 2012192370 A JP2012192370 A JP 2012192370A JP 2013079941 A5 JP2013079941 A5 JP 2013079941A5
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Japan
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integrated circuit
test
interconnect
signal
instruction
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JP2012192370A
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Japanese (ja)
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JP6233948B2 (ja
JP2013079941A (ja
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Priority claimed from US13/250,368 external-priority patent/US9110142B2/en
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JP2012192370A 2011-09-30 2012-08-31 集積回路およびその動作方法 Expired - Fee Related JP6233948B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/250,368 US9110142B2 (en) 2011-09-30 2011-09-30 Methods and apparatus for testing multiple-IC devices
US13/250,368 2011-09-30

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2017133640A Division JP2017194483A (ja) 2011-09-30 2017-07-07 マルチｉｃデバイスをテストするための方法および装置

Publications (3)

Publication Number Publication Date
JP2013079941A JP2013079941A (ja) 2013-05-02
JP2013079941A5 true JP2013079941A5 (enExample) 2015-10-01
JP6233948B2 JP6233948B2 (ja) 2017-11-22

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JP2012192370A Expired - Fee Related JP6233948B2 (ja) 2011-09-30 2012-08-31 集積回路およびその動作方法
JP2017133640A Withdrawn JP2017194483A (ja) 2011-09-30 2017-07-07 マルチｉｃデバイスをテストするための方法および装置

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JP2017133640A Withdrawn JP2017194483A (ja) 2011-09-30 2017-07-07 マルチｉｃデバイスをテストするための方法および装置

Country Status (4)

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US (1) US9110142B2 (enExample)
EP (2) EP2574945B1 (enExample)
JP (2) JP6233948B2 (enExample)
CN (1) CN103033736B (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6115042B2 (ja) * 2012-08-27 2017-04-19 富士通株式会社 情報処理装置、テストデータ作成装置、テストデータ作成方法、およびプログラム
US9106575B2 (en) * 2013-01-31 2015-08-11 Apple Inc. Multiplexing multiple serial interfaces
CN104237772A (zh) * 2013-06-24 2014-12-24 英业达科技有限公司 除错系统
US9213063B2 (en) * 2014-03-26 2015-12-15 Freescale Semiconductor, Inc. Reset generation circuit for scan mode exit
US9772376B1 (en) * 2016-04-29 2017-09-26 Texas Instruments Incorporated Increase data transfer throughput by enabling dynamic JTAG test mode entry and sharing of all JTAG pins
US9791505B1 (en) * 2016-04-29 2017-10-17 Texas Instruments Incorporated Full pad coverage boundary scan
CN106230431B (zh) * 2016-08-04 2019-05-14 浪潮电子信息产业股份有限公司 一种引脚复用方法及cpld芯片
CN106443408B (zh) * 2016-08-30 2019-06-14 无锡华润矽科微电子有限公司 实现单端口多功能复用的用于集成电路测试的电路结构
CN106844285B (zh) * 2017-01-20 2020-11-03 中颖电子股份有限公司 一种mcu芯片架构系统
CN109406902B (zh) * 2018-11-28 2021-03-19 中科曙光信息产业成都有限公司 逻辑扫描老化测试系统
CN109581197A (zh) * 2018-12-28 2019-04-05 中国电子科技集团公司第五十八研究所 一种基于JTAG接口的SiP封装用测试系统
CN110347139A (zh) * 2019-05-22 2019-10-18 苏州浪潮智能科技有限公司 一种i2c总线的测试治具
CN112578272A (zh) * 2019-09-30 2021-03-30 深圳市中兴微电子技术有限公司 一种jtag控制装置及实现jtag控制的方法
JP7310629B2 (ja) * 2020-01-31 2023-07-19 富士通株式会社 リセット制御回路およびリセット制御回路によるリセット方法
US11199582B2 (en) * 2020-04-06 2021-12-14 Xilinx, Inc. Implementing a JTAG device chain in multi-die integrated circuit
CN111752780B (zh) * 2020-06-12 2023-03-21 苏州浪潮智能科技有限公司 一种服务器jtag部件自适应互连系统、方法
CN111966077A (zh) * 2020-08-13 2020-11-20 格力电器（合肥）有限公司 测试设备及测试方法
CN112526327B (zh) * 2020-10-28 2022-07-08 深圳市紫光同创电子有限公司 边界扫描测试方法及存储介质
CN114253184B (zh) * 2021-11-29 2025-01-03 山东云海国创云计算装备产业创新中心有限公司 一种jtag控制装置
CN114597195A (zh) * 2022-03-02 2022-06-07 上海壁仞智能科技有限公司 多芯片系统以及多芯片系统的操作方法
US12092690B2 (en) * 2022-12-31 2024-09-17 Siliconch Systems Pvt Ltd Emulation of JTAG/SCAN test interface protocols using SPI communication device
US20240331461A1 (en) * 2023-03-27 2024-10-03 B/E Aerospace, Inc. Universal communication node
TWI881599B (zh) * 2023-12-14 2025-04-21 英業達股份有限公司 提供不同類型連接介面的通用檢測系統及其方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5056093A (en) * 1989-08-09 1991-10-08 Texas Instruments Incorporated System scan path architecture
US6324662B1 (en) 1996-08-30 2001-11-27 Texas Instruments Incorporated TAP and linking module for scan access of multiple cores with IEEE 1149.1 test access ports
US7590910B2 (en) 1998-03-27 2009-09-15 Texas Instruments Incorporated Tap and linking module for scan access of multiple cores with IEEE 1149.1 test access ports
US5768289A (en) * 1997-05-22 1998-06-16 Intel Corporation Dynamically controlling the number of boundary-scan cells in a boundary-scan path
JP3659772B2 (ja) * 1997-08-07 2005-06-15 三菱自動車工業株式会社 バッテリの劣化判定装置
US6115836A (en) * 1997-09-17 2000-09-05 Cypress Semiconductor Corporation Scan path circuitry for programming a variable clock pulse width
US6125464A (en) 1997-10-16 2000-09-26 Adaptec, Inc. High speed boundary scan design
JP3980827B2 (ja) * 2000-03-10 2007-09-26 株式会社ルネサステクノロジ 半導体集積回路装置および製造方法
US7089463B1 (en) * 2002-02-20 2006-08-08 Cisco Technology Inc. Test buffer design and interface mechanism for differential receiver AC/DC boundary scan test
US7346821B2 (en) * 2003-08-28 2008-03-18 Texas Instrument Incorporated IC with JTAG port, linking module, and off-chip TAP interface
EP1544632B1 (en) * 2003-12-17 2008-08-27 STMicroelectronics (Research & Development) Limited TAP sampling at double rate
US7490231B2 (en) * 2004-07-23 2009-02-10 Broadcom Corporation Method and system for blocking data in scan registers from being shifted out of a device
US7818640B1 (en) 2004-10-22 2010-10-19 Cypress Semiconductor Corporation Test system having a master/slave JTAG controller
CN101065679B (zh) * 2004-11-22 2010-09-01 飞思卡尔半导体公司 集成电路及用于测试多tap集成电路的方法
US7552360B2 (en) * 2005-03-21 2009-06-23 Texas Instruments Incorporated Debug and test system with format select register circuitry
US7536597B2 (en) * 2005-04-27 2009-05-19 Texas Instruments Incorporated Apparatus and method for controlling power, clock, and reset during test and debug procedures for a plurality of processor/cores
TW200708750A (en) * 2005-07-22 2007-03-01 Koninkl Philips Electronics Nv Testable integrated circuit, system in package and test instruction set
ATE436029T1 (de) * 2005-10-26 2009-07-15 Nxp Bv Analog-ic mit testanordnung und testverfahren für ein solches ic
US20090019328A1 (en) 2006-03-01 2009-01-15 Koninklijke Philips Electronics N.V. Ic circuit with test access control circuit using a jtag interface
US20090222251A1 (en) * 2006-10-31 2009-09-03 International Business Machines Corporation Structure For An Integrated Circuit That Employs Multiple Interfaces
US7945831B2 (en) 2008-10-31 2011-05-17 Texas Instruments Incorporated Gating TDO from plural JTAG circuits
US8275977B2 (en) * 2009-04-08 2012-09-25 Freescale Semiconductor, Inc. Debug signaling in a multiple processor data processing system
DE102010002460A1 (de) * 2010-03-01 2011-09-01 Robert Bosch Gmbh Verfahren zum Testen eines integrierten Schaltkreises

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