JP2013069734A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 239000002344 surface layer Substances 0.000 claims abstract description 10
- 230000000694 effects Effects 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 29
- 238000000034 method Methods 0.000 description 29
- 238000010586 diagram Methods 0.000 description 20
- 238000004519 manufacturing process Methods 0.000 description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000001020 plasma etching Methods 0.000 description 8
- 230000005684 electric field Effects 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
Abstract
【解決手段】実施形態の半導体装置は、半導体基板において素子分離領域によって仕切られた素子領域と、前記素子領域を横切る所定の方向に沿って前記素子領域の表層に設けられたゲートトレンチにより分離されて前記素子領域の表層に形成されたソース領域およびドレイン領域とを備える。また、実施形態の半導体装置は、少なくとも一部が前記ゲートトレンチ内にゲート絶縁膜を介して埋め込まれて前記ソース領域およびドレイン領域よりも深い位置まで形成されたゲート電極を備える。ドレイン領域における前記ゲート絶縁膜と接触する界面は、前記ゲート電極側に突出した凸部を有する。
【選択図】図2
Description
図1は、第1の実施の形態にかかるリセスチャネル型トランジスタTr1(以下、トランジスタTr1と呼ぶ場合がある)の構造を模式的示す平面図である。図2は、第1の実施の形態にかかるリセスチャネル型トランジスタTr1の構造を模式的に示す図であり、図2(a)は図1のA−A’線に沿う要部縦断面図、図2(b)は図1のB−B’線に沿う要部縦断面図、図2(c)は図2(a)のC−C’線に沿う要部横断面図である。なお、図1においては、半導体基板10、素子領域11、不純物拡散層であるソース・ドレイン領域16およびゲート電極15に注目して示しており、その他の部材の図示を省略している。
図11は、第2の実施の形態にかかるリセスチャネル型トランジスタTr2(以下、トランジスタTr2と呼ぶ場合がある)の構造を模式的に示す図であり、図11(a)は図2(a)に対応する要部縦断面図、図11(b)は図2(b)に対応する要部縦断面図、図11(c)は図2(c)に対応する要部横断面図である。第2の実施の形態にかかるリセスチャネル型トランジスタTr2は、ゲートトレンチ13の円弧状領域に形成されたゲート絶縁膜14と接触する半導体基板10の形状以外は、第1の実施の形態にかかるリセスチャネル型トランジスタTr1と同じ構造を有する。以下では、第1の実施の形態にかかるリセスチャネル型トランジスタTr1と異なる点について説明する。なお、第2の実施の形態において示す図面では、第1の実施の形態の場合と同じ部材については同じ符号を付すことで説明を省略する。
Claims (6)
- 半導体基板において素子分離領域によって仕切られた素子領域と、
前記素子領域を横切る所定の方向に沿って前記素子領域の表層に設けられたゲートトレンチにより分離されて前記素子領域の表層に形成されたソース領域およびドレイン領域と、
少なくとも一部が前記ゲートトレンチ内にゲート絶縁膜を介して埋め込まれて前記ソース領域およびドレイン領域よりも深い位置まで形成されたゲート電極と、
を備え、
前記ゲートトレンチは、前記所定の方向において前記ソース領域および前記ドレイン領域間よりも幅広な領域を前記ソース領域および前記ドレイン領域よりも深い位置に有し、
前記ゲート絶縁膜は、前記ドレイン領域の界面に接触する領域の厚みが、前記幅広な領域の内壁に接触する領域の厚みよりも厚く、
前記ドレイン領域における前記ゲート絶縁膜と接触する界面が、前記ゲート電極側に突出した凸部を前記半導体基板の厚み方向の全幅にわたって有し、
前記素子領域において前記ソース領域および前記ドレイン領域よりも深い位置の前記ゲート絶縁膜と接触する前記半導体基板の界面が、前記ゲート電極側に突出する凸部を有すること、
を特徴とする半導体装置。 - 半導体基板において素子分離領域によって仕切られた素子領域と、
前記素子領域を横切る所定の方向に沿って前記素子領域の表層に設けられたゲートトレンチにより分離されて前記素子領域の表層に形成されたソース領域およびドレイン領域と、
少なくとも一部が前記ゲートトレンチ内にゲート絶縁膜を介して埋め込まれて前記ソース領域およびドレイン領域よりも深い位置まで形成されたゲート電極と、
を備え、
前記ドレイン領域における前記ゲート絶縁膜と接触する界面は、前記ゲート電極側に突出した凸部を有すること、
を特徴とする半導体装置。 - 前記凸部は、前記ドレイン領域の界面において、前記半導体基板の厚み方向の全幅にわたって設けられること、
を特徴とする請求項2に記載の半導体装置。 - 前記ゲートトレンチは、前記所定の方向において前記ソース領域および前記ドレイン領域間よりも幅広な領域を前記ソース領域および前記ドレイン領域よりも深い位置に有し、
前記ゲート絶縁膜は、前記ドレイン領域の界面に接触する領域の厚みが、前記幅広な領域の内壁に接触する領域の厚みよりも厚いこと、
を特徴とする請求項2または3に記載の半導体装置。 - 前記凸部は、前記半導体基板の面方向において前記ゲート電極側に突出した三角形状、台形状および円弧状のうちのいずれか1つの形状を有すること、
を特徴とする請求項2〜4のいずれか1つに記載の半導体装置。 - 前記素子領域において前記ソース領域および前記ドレイン領域よりも深い位置の前記ゲート絶縁膜と接触する前記半導体基板の界面が、前記ゲート電極側に突出する凸部を有すること、
を特徴とする請求項2〜5のいずれか1つに記載の半導体装置。
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JP2011205452A JP5547152B2 (ja) | 2011-09-21 | 2011-09-21 | 半導体装置 |
US13/601,400 US8680612B2 (en) | 2011-09-21 | 2012-08-31 | Semiconductor device and manufacturing method thereof |
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JP2011205452A JP5547152B2 (ja) | 2011-09-21 | 2011-09-21 | 半導体装置 |
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JP2013069734A true JP2013069734A (ja) | 2013-04-18 |
JP5547152B2 JP5547152B2 (ja) | 2014-07-09 |
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US8865549B2 (en) | 2012-12-07 | 2014-10-21 | Texas Instruments Incorporated | Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length |
US11695051B2 (en) * | 2019-03-29 | 2023-07-04 | Intel Corporation | Gate stacks for FinFET transistors |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006054431A (ja) * | 2004-06-29 | 2006-02-23 | Infineon Technologies Ag | トランジスタ、メモリセルアレイ、および、トランジスタ製造方法 |
JP2007049121A (ja) * | 2005-08-09 | 2007-02-22 | Infineon Technologies Ag | 半導体構造の形成方法及び形成方法に対応する半導体構造 |
JP2007201396A (ja) * | 2006-01-23 | 2007-08-09 | Hynix Semiconductor Inc | 半導体素子及びその製造方法 |
JP2008135458A (ja) * | 2006-11-27 | 2008-06-12 | Elpida Memory Inc | 半導体装置及びその製造方法 |
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US7189617B2 (en) | 2005-04-14 | 2007-03-13 | Infineon Technologies Ag | Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor |
US7902597B2 (en) * | 2006-03-22 | 2011-03-08 | Samsung Electronics Co., Ltd. | Transistors with laterally extended active regions and methods of fabricating same |
KR100835278B1 (ko) * | 2006-06-28 | 2008-06-05 | 삼성전자주식회사 | 리세스-핀 트랜지스터를 갖는 반도체 소자 및 그 제조방법 |
US20080012067A1 (en) | 2006-07-14 | 2008-01-17 | Dongping Wu | Transistor and memory cell array and methods of making the same |
JP4446202B2 (ja) | 2006-09-22 | 2010-04-07 | エルピーダメモリ株式会社 | 半導体装置及び半導体装置の製造方法 |
US7795096B2 (en) * | 2006-12-29 | 2010-09-14 | Qimonda Ag | Method of forming an integrated circuit with two types of transistors |
KR100843879B1 (ko) * | 2007-03-15 | 2008-07-03 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
KR101374335B1 (ko) * | 2007-09-10 | 2014-03-17 | 삼성전자주식회사 | 국부적으로 두꺼운 유전막을 갖는 리세스 채널트랜지스터의 제조방법 및 관련된 소자 |
JP2010003916A (ja) | 2008-06-20 | 2010-01-07 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US9190495B2 (en) * | 2008-09-22 | 2015-11-17 | Samsung Electronics Co., Ltd. | Recessed channel array transistors, and semiconductor devices including a recessed channel array transistor |
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---|---|---|---|---|
JP2006054431A (ja) * | 2004-06-29 | 2006-02-23 | Infineon Technologies Ag | トランジスタ、メモリセルアレイ、および、トランジスタ製造方法 |
JP2007049121A (ja) * | 2005-08-09 | 2007-02-22 | Infineon Technologies Ag | 半導体構造の形成方法及び形成方法に対応する半導体構造 |
JP2007201396A (ja) * | 2006-01-23 | 2007-08-09 | Hynix Semiconductor Inc | 半導体素子及びその製造方法 |
JP2008135458A (ja) * | 2006-11-27 | 2008-06-12 | Elpida Memory Inc | 半導体装置及びその製造方法 |
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