JP2013038301A - 半導体装置および半導体装置の製造方法 - Google Patents
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
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Abstract
【解決手段】半導体基板1上に支柱型半導体4を形成し、支柱型半導体4の下部を埋め込む絶縁層5を半導体基板1上に形成し、支柱型半導体4の上部の側面に接合されたフィン型半導体6を絶縁層5上に形成し、フィン型半導体6を絶縁層5上に残したまま支柱型半導体4を除去する。
【選択図】 図6
Description
前者のタイプのフィン型トランジスタでは、ソース/ドレイン間のリーク電流防止のためフィンチャネルボトムにパンチスルーストッパが必要で、パンチスルーストッパ形成時にチャネルに不純物がドーピングされてしまいチャネル不純物濃度が高くなってしまうことが問題である。
図1(a)〜図17(a)は、第1実施形態に係る半導体装置の概略構成を示す平面図、図1(b)〜図17(b)および図17(c)は、第1実施形態に係る半導体装置の概略構成を示す断面図である。図1(c)は、半導体層2の深さ方向のGe濃度分布を示す図である。なお、図1(b)〜図17(b)は、図1(a)〜図17(a)のA−A線でそれぞれ切断した断面図、図17(c)は、図17(a)のB−B線で切断した断面図である。
図18(a)および図18(b)は、第2実施形態に係る半導体装置の製造方法を示す断面図である。
図18(a)において、半導体基板21上に支柱型半導体24を形成し、支柱型半導体24の下部が埋め込まれるように埋め込み絶縁層22を半導体基板21上に形成する。この時、支柱型半導体24上にはハードマスク層23が形成されている。
図19(a)〜図23(a)は、第3実施形態に係る半導体装置の概略構成を示す平面図、図19(b)〜図23(b)および図23(c)は、第3実施形態に係る半導体装置の概略構成を示す断面図である。なお、図19(b)〜図23(b)は、図19(a)〜図23(a)のA−A線でそれぞれ切断した断面図、図23(c)は、図23(a)のB−B線で切断した断面図である。
図24(a)〜図38(a)は、第4実施形態に係る半導体装置の概略構成を示す平面図、図24(b)〜図38(b)および図38(c)は、第4実施形態に係る半導体装置の概略構成を示す断面図である。なお、図24(b)〜図38(b)は、図24(a)〜図38(a)のA−A線でそれぞれ切断した断面図、図38(c)は、図38(a)のB−B線で切断した断面図である。
Claims (5)
- 半導体基板上に支柱型半導体を形成する工程と、
前記支柱型半導体の下部を埋め込む絶縁層を前記半導体基板上に形成する工程と、
前記支柱型半導体の上部の側面に接合されたフィン型半導体を前記絶縁層上に形成する工程と、
前記フィン型半導体を前記絶縁層上に残したまま前記絶縁層上の前記支柱型半導体を除去する工程とを備えることを特徴とする半導体装置の製造方法。 - 前記支柱型半導体は前記フィン型半導体よりもエッチングレートの高い材料にて構成されていることを特徴とする請求項1に記載の半導体装置の製造方法。
- 互いにエッチングレートの異なる第1および第2のフィン型半導体を前記支柱型半導体の横方向に交互に繰り返して前記絶縁層上に形成することを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 選択エピタキシャル成長にて半導体基板上に半導体層を形成する工程と、
前記半導体層上にハードマスク層を形成する工程と、
前記ハードマスク層をマスクとして前記半導体層をエッチングすることにより、前記半導体基板上に支柱型半導体を形成する工程と、
前記支柱型半導体の下部を埋め込む絶縁層を前記半導体基板上に形成する工程と、
前記支柱型半導体の上部の側面に接合されたフィン型半導体を前記絶縁層上に形成する工程と、
前記ハードマスク層および前記フィン型半導体を覆う保護膜を前記絶縁層上に形成する工程と、
前記フィン型半導体を前記保護膜で覆ったまま前記ハードマスク層の表面を前記保護膜から露出させる工程と、
前記ハードマスク層を除去することにより、前記支柱型半導体の表面を露出させる工程と、
前記ハードマスク層が除去された前記支柱型半導体の異方性エッチングにて前記支柱型半導体を除去する工程とを備えることを特徴とする半導体装置の製造方法。 - チャネルとして用いる二つの対向する側面の表面ラフネスが異なるフィン型半導体と、前記フィン型半導体の側面にゲート絶縁膜を介して形成されたゲート電極と、
前記フィン型半導体の両端部に形成されたソース/ドレインとを備えることを特徴とする半導体装置。
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