JP2012522369A - ソース／ドレイン延長部、ハローポケット及びゲート誘電体厚さの異なる構成を有する同極性の電界効果トランジスタの構成及び製造 - Google Patents

ソース／ドレイン延長部、ハローポケット及びゲート誘電体厚さの異なる構成を有する同極性の電界効果トランジスタの構成及び製造 Download PDF

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JP2012522369A
JP2012522369A JP2012502017A JP2012502017A JP2012522369A JP 2012522369 A JP2012522369 A JP 2012522369A JP 2012502017 A JP2012502017 A JP 2012502017A JP 2012502017 A JP2012502017 A JP 2012502017A JP 2012522369 A JP2012522369 A JP 2012522369A
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fet
extension
dopant
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JP2012522369A5 (enExample
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コンスタンチン ブルシー，
ウイリアム ディー． フレンチ，
ドナルド エム． アーチャー，
ジャン−ジーウン ヤン，
サンディープ アール． バール，
ディー． コートニー パーカー，
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National Semiconductor Corp
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National Semiconductor Corp
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  • Physics & Mathematics (AREA)
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  • High Energy & Nuclear Physics (AREA)
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  • Manufacturing & Machinery (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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JP2012502017A 2009-03-27 2010-03-25 ソース／ドレイン延長部、ハローポケット及びゲート誘電体厚さの異なる構成を有する同極性の電界効果トランジスタの構成及び製造 Pending JP2012522369A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/382,971 US8084827B2 (en) 2009-03-27 2009-03-27 Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses
US12/382,971 2009-03-27
PCT/US2010/000898 WO2010110902A1 (en) 2009-03-27 2010-03-25 Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses

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JP2012522369A true JP2012522369A (ja) 2012-09-20
JP2012522369A5 JP2012522369A5 (enExample) 2013-05-09

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US (2) US8084827B2 (enExample)
EP (1) EP2412016A4 (enExample)
JP (1) JP2012522369A (enExample)
KR (1) KR20110133622A (enExample)
CN (1) CN102365730A (enExample)
TW (1) TW201101463A (enExample)
WO (1) WO2010110902A1 (enExample)

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US8482076B2 (en) * 2009-09-16 2013-07-09 International Business Machines Corporation Method and structure for differential silicide and recessed or raised source/drain to improve field effect transistor
US20110291193A1 (en) * 2010-05-27 2011-12-01 International Business Machines Corporation High density butted junction cmos inverter, and making and layout of same
JP6043193B2 (ja) * 2013-01-28 2016-12-14 株式会社東芝 トンネルトランジスタ
KR102180554B1 (ko) 2013-12-04 2020-11-19 삼성디스플레이 주식회사 박막 트랜지스터 및 이의 제조 방법
US9324783B2 (en) * 2014-09-30 2016-04-26 Infineon Technologies Ag Soft switching semiconductor device and method for producing thereof
CN109980009B (zh) * 2017-12-28 2020-11-03 无锡华润上华科技有限公司 一种半导体器件的制造方法和集成半导体器件
CN109980010B (zh) * 2017-12-28 2020-10-13 无锡华润上华科技有限公司 一种半导体器件的制造方法和集成半导体器件
FR3099638A1 (fr) * 2019-07-31 2021-02-05 Stmicroelectronics (Rousset) Sas Procédé de fabrication comprenant une définition d’une longueur effective de canal de transistors MOSFET
US11455452B2 (en) * 2019-09-23 2022-09-27 Texas Instruments Incorporated Variable implant and wafer-level feed-forward for dopant dose optimization
CN111785777B (zh) * 2020-06-28 2023-10-20 上海华虹宏力半导体制造有限公司 高压cmos器件及其制造方法

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