JP2012519374A - 底部で減少する直径を有する金属ピラーを含む半導体デバイスのメタライゼーションシステム - Google Patents

底部で減少する直径を有する金属ピラーを含む半導体デバイスのメタライゼーションシステム Download PDF

Info

Publication number
JP2012519374A
JP2012519374A JP2011551432A JP2011551432A JP2012519374A JP 2012519374 A JP2012519374 A JP 2012519374A JP 2011551432 A JP2011551432 A JP 2011551432A JP 2011551432 A JP2011551432 A JP 2011551432A JP 2012519374 A JP2012519374 A JP 2012519374A
Authority
JP
Japan
Prior art keywords
passivation layer
opening
semiconductor device
lateral dimension
metal pillar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011551432A
Other languages
English (en)
Japanese (ja)
Other versions
JP2012519374A5 (enExample
Inventor
フォイステル フランク
フローベルク カイ
ワーナー トーマス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2012519374A publication Critical patent/JP2012519374A/ja
Publication of JP2012519374A5 publication Critical patent/JP2012519374A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01233—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01235—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01257—Changing the shapes of bumps by reflowing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/234—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H10W72/9232—Bond pads having multiple stacked layers with additional elements interposed between layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
JP2011551432A 2009-02-27 2010-02-22 底部で減少する直径を有する金属ピラーを含む半導体デバイスのメタライゼーションシステム Pending JP2012519374A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102009010885.8A DE102009010885B4 (de) 2009-02-27 2009-02-27 Metallisierungssystem eines Halbleiterbauelements mit Metallsäulen mit einem kleineren Durchmesser an der Unterseite und Herstellungsverfahren dafür
DE102009010885.8 2009-02-27
PCT/EP2010/001092 WO2010097191A1 (en) 2009-02-27 2010-02-22 A metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom

Publications (2)

Publication Number Publication Date
JP2012519374A true JP2012519374A (ja) 2012-08-23
JP2012519374A5 JP2012519374A5 (enExample) 2013-04-11

Family

ID=42102254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011551432A Pending JP2012519374A (ja) 2009-02-27 2010-02-22 底部で減少する直径を有する金属ピラーを含む半導体デバイスのメタライゼーションシステム

Country Status (6)

Country Link
US (1) US9245860B2 (enExample)
JP (1) JP2012519374A (enExample)
KR (1) KR20110128897A (enExample)
CN (1) CN102428551A (enExample)
DE (1) DE102009010885B4 (enExample)
WO (1) WO2010097191A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8314472B2 (en) 2010-07-29 2012-11-20 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Semiconductor structure comprising pillar
US8344504B2 (en) 2010-07-29 2013-01-01 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Semiconductor structure comprising pillar and moisture barrier
US20120273937A1 (en) * 2011-04-30 2012-11-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer
US8536707B2 (en) 2011-11-29 2013-09-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Semiconductor structure comprising moisture barrier and conductive redistribution layer
US9768142B2 (en) 2013-07-17 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming bonding structures
US10049893B2 (en) 2016-05-11 2018-08-14 Advanced Semiconductor Engineering, Inc. Semiconductor device with a conductive post
US10636758B2 (en) 2017-10-05 2020-04-28 Texas Instruments Incorporated Expanded head pillar for bump bonds
KR102940785B1 (ko) 2020-03-26 2026-03-20 삼성전자주식회사 반도체 패키지
US12660670B2 (en) * 2022-09-13 2026-06-16 Micron Technology, Inc. Integrated circuit device with embedded metal pads

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0555228A (ja) * 1991-08-27 1993-03-05 Nec Corp 半導体装置
JPH05206139A (ja) * 1991-11-19 1993-08-13 Nec Corp 基板接続電極およびその製造方法
JP2000228420A (ja) * 1999-02-05 2000-08-15 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2002076046A (ja) * 2000-09-04 2002-03-15 Citizen Watch Co Ltd 半導体装置の製造方法
JP2006295109A (ja) * 2005-03-14 2006-10-26 Citizen Watch Co Ltd 半導体装置とその製造方法
JP2010525553A (ja) * 2007-02-28 2010-07-22 ネペス コーポレーション 半導体装置のバンプ構造

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5137597A (en) * 1991-04-11 1992-08-11 Microelectronics And Computer Technology Corporation Fabrication of metal pillars in an electronic component using polishing
JP2773578B2 (ja) * 1992-10-02 1998-07-09 日本電気株式会社 半導体装置の製造方法
US5656858A (en) * 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
US5912510A (en) * 1996-05-29 1999-06-15 Motorola, Inc. Bonding structure for an electronic device
US5773897A (en) * 1997-02-21 1998-06-30 Raytheon Company Flip chip monolithic microwave integrated circuit with mushroom-shaped, solder-capped, plated metal bumps
US5891756A (en) * 1997-06-27 1999-04-06 Delco Electronics Corporation Process for converting a wire bond pad to a flip chip solder bump pad and pad formed thereby
JP3420703B2 (ja) * 1998-07-16 2003-06-30 株式会社東芝 半導体装置の製造方法
US6103552A (en) * 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
TWI244129B (en) * 2002-10-25 2005-11-21 Via Tech Inc Bonding column process
JP4119866B2 (ja) * 2004-05-12 2008-07-16 富士通株式会社 半導体装置
TWI242253B (en) * 2004-10-22 2005-10-21 Advanced Semiconductor Eng Bumping process and structure thereof
US8709934B2 (en) * 2007-06-05 2014-04-29 Stats Chippac Ltd. Electronic system with vertical intermetallic compound

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0555228A (ja) * 1991-08-27 1993-03-05 Nec Corp 半導体装置
JPH05206139A (ja) * 1991-11-19 1993-08-13 Nec Corp 基板接続電極およびその製造方法
JP2000228420A (ja) * 1999-02-05 2000-08-15 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2002076046A (ja) * 2000-09-04 2002-03-15 Citizen Watch Co Ltd 半導体装置の製造方法
JP2006295109A (ja) * 2005-03-14 2006-10-26 Citizen Watch Co Ltd 半導体装置とその製造方法
JP2010525553A (ja) * 2007-02-28 2010-07-22 ネペス コーポレーション 半導体装置のバンプ構造

Also Published As

Publication number Publication date
US20100219527A1 (en) 2010-09-02
DE102009010885A1 (de) 2010-09-02
US9245860B2 (en) 2016-01-26
DE102009010885B4 (de) 2014-12-31
KR20110128897A (ko) 2011-11-30
CN102428551A (zh) 2012-04-25
WO2010097191A1 (en) 2010-09-02

Similar Documents

Publication Publication Date Title
CN113658944B (zh) 半导体封装件及其形成方法
CN110034026B (zh) 封装件结构和方法
TWI718722B (zh) 接合結構及其形成方法
US8039958B2 (en) Semiconductor device including a reduced stress configuration for metal pillars
US8994188B2 (en) Interconnect structures for substrate
TWI822153B (zh) 封裝結構及其形成方法
TW202123413A (zh) 具有接合結構的裝置及封裝及形成接合結構的方法
US9245860B2 (en) Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom
KR20190024570A (ko) 반도체 패키지 내의 도전성 비아 및 그 형성 방법
US8482123B2 (en) Stress reduction in chip packaging by using a low-temperature chip-package connection regime
US20110024900A1 (en) Semiconductor device including a stress buffer material formed above a low-k metallization system
US20100164098A1 (en) Semiconductor device including a cost-efficient chip-package connection based on metal pillars
TWI773400B (zh) 半導體元件及其製造方法
TW202543078A (zh) 半導體晶粒的封裝結構及其形成方法
CN115763272B (zh) 半导体元件及其制备方法
US20130140696A1 (en) Semiconductor device
TW202137354A (zh) 半導體裝置及其形成方法
TWI825572B (zh) 晶片封裝結構及其形成方法
CN222261042U (zh) 半导体封装件
US8786088B2 (en) Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction
CN223284980U (zh) 半导体装置
WO2010049087A2 (en) A semiconductor device including a reduced stress configuration for metal pillars
US20240312857A1 (en) Semiconductor structure and method of fabricating same
TWI483314B (zh) 通過裝設附加保護層以在運送期間保護半導體裝置的反應性金屬表面的技術
TW202449922A (zh) 封裝件結構和其形成方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130221

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130221

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20131216

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140205

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140507

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140625