CN102428551A - 包含底部有直径缩减的金属支柱的半导体器件的金属化系统 - Google Patents

包含底部有直径缩减的金属支柱的半导体器件的金属化系统 Download PDF

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CN102428551A
CN102428551A CN2010800183996A CN201080018399A CN102428551A CN 102428551 A CN102428551 A CN 102428551A CN 2010800183996 A CN2010800183996 A CN 2010800183996A CN 201080018399 A CN201080018399 A CN 201080018399A CN 102428551 A CN102428551 A CN 102428551A
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metal
lateral dimension
passivation layer
semiconductor device
opening
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F·福斯特
K·弗罗贝格
T·沃纳
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Abstract

在复杂半导体器件的金属化系统中，可以钉状组态来形成金属支柱(271)，例如铜支柱，以便减少作用于该金属化系统的最大机械应力，同时提供连接至封装基板的必要接触面。基于经适当组态的抗蚀剂掩膜，可得到该钉状组态。

Description

包含底部有直径缩减的金属支柱的半导体器件的金属化系统
技术领域
本揭示内容大体有关于有包含金属支柱的金属化系统的集成电路，且更特别的是有关于用以减少由芯片与封装件间的热失配(thermal mismatch)造成的芯片-封装件相互作用的技术。
背景技术
半导体器件通常在由任何适当材料制成的实质圆盘形基板上形成。目前以及在可预见的未来，会基于硅来制造含有高度复杂电子电路的大多数半导体器件，从而致使硅基板及含硅基板(例如，SOI(绝缘层上覆硅)基板)成为用于形成半导体器件(例如，微处理器、SRAM、ASIC(特殊应用集成电路)、系统单芯片(SoC)、及其类似者)的可行基材。个别集成电路于晶片上排列成阵列，其中，除了微影制程、量测制程以及在基板切片后个别组件的封装以外，对于基板的所有芯片区同时进行大部份的制造步骤(可能包含数百个个别制程步骤，而且在精密集成电路中会更多)。因此，经济约束驱策半导体制造商稳定地增加基板尺寸，从而也增加可用来生产实际半导体器件的面积及提高生产良率。
除了增加基板面积以外，也很重要的是，在给定基板尺寸下，优化基板面积的利用以便实际尽可能地让基板面积用于半导体器件及/或可用于制程控制的测试结构。在尝试最大化给定基板尺寸的有用表面积时，电路组件的特征尺寸被稳定地缩小比例。由于有缩减高度精密半导体器件之特征尺寸的持续需求，与低介电常数电介质材料组合的铜已变成在形成包含金属线路层及中间导通孔层(via layer)的所谓互连结构时常用的替代物，该导通孔层包括作为层内连线(intra-layer connection)的金属线路与作为层间连线(inter-layerconnection)的导通孔，这些通常连接个别的电路组件以提供集成电路的必要机能。通常，多个金属线路层及导通孔层需要彼此迭在上面以实现所考量的电路设计里的所有内部电路组件与I/O(输入/输出)之间的连线、电源垫与接地垫。
至于被极端缩放的集成电路，讯号传播延迟不再受限于电路组件，例如场效应晶体管及其类似者，反而由于增加电路组件的密度需要增加更多条电气连线而受限于紧邻的金属线路，因为线间电容(line-to-line capacitance)会增加而且线路的导电率也因横截面面积减少而减少。因此之故，用有较低介电参数的电介质材料来取代传统电介质，例如二氧化硅(k＞4)及氮化硅(k＞7)，因此被称作相对介电参数等于3或更小的低介电常数电介质。不过，相较于众所公认的电介质(二氧化硅及氮化硅)，低介电常数材料的密度及机械稳定性或强度明显较低。结果，在形成金属化系统以及任何后续的集成电路制程期间，生产良率可能取决于敏感电介质材料(例如，低介电常数介电层)的机械特性，及与其它材料的粘着性。
除了电介质常数等于3.0及更小的先进电介质材料有机械稳定性降低的问题以外，在精密半导体器件操作期间，这些材料可能影响组件可靠性，因为不同材料的对应热膨胀之热失配会导致芯片与封装件相互作用。例如，在复杂集成电路的制造中，越来越多习知为覆晶(flipchip)封装技术的接触技术可用来连接封装件载具至芯片。公认有效的焊线技术是可将适当接触垫安置于芯片之最后一个金属层中可用导线连接至封装件之对应端子的周边，相反地，在覆晶技术，可形成个别的凸块结构于例如由焊料构成可与封装件之个别接触垫接触的最后金属化层上。因此，在回焊凸块材料后，在最后金属化层与封装件载具的接触垫之间可建立可靠的电气及机械连线。以此方式，可以减少接触电阻及寄生电容的方式装设跨越最后金属化层整个芯片区的极大量电气连线，从而提供复杂集成电路(例如，CPU、存储器及其类似者)所需的IO(输入/输出)能力。在连接凸块结构与封装件载具的对应制程顺序期间，可施加某一程度的压力及/或热至复合器件以便在形成于芯片上的每个凸块与可设在封装基板上的凸块或垫之间建立可靠的连线。不过，热或机械诱发应力可能作用于较低的金属化层(通常包含低介电常数电介质甚至超低介电常数(ULK)电介质材料)，从而通过敏感材料因机械稳定性与对于其它材料的粘着性减少引起的脱层(delamination)而显着提高产生缺陷的机率。
此外，在附着至对应封装基板之完成的半导体器件的操作期间，硅基半导体芯片与封装基板之热膨胀特性的明显失配也可能出现显着的机械应力，因为在量产精密集成电路时，经济约束通常要求使用特定的基板材料于封装件，例如有机材料，它们通常与硅芯片有不同的导热性及不同的热膨胀系数。
在最近的发展中，替换或者除了焊锡凸块或球以外，通过装设铜支柱来提高“凸块结构”的热及电气效能，从而减少个别接触组件的必要占地面积(floor space)而且由于铜有优于常用焊料的特性也可增强热及电气导电率。不过，铜支柱可能在封装件与芯片的金属化系统之间造成更加严重的相互作用，因为相较于凸块结构，通常铜支柱显然比较不会变形，这在电气及热特性方面是有利的，不过，可能以局部极受限的方式导致机械应力分量增加，在说明图1a及1b时会有更详细的描述。
图1a的横截面图示意图示包含连接至封装基板180之半导体晶粒或芯片100的集成电路150，封装基板180实质由有机材料构成，例如适当的聚合物材料及其类似者，其中用支柱结构170可实现芯片100与封装基板180之间的连线。半导体芯片100通常可包含基板101，例如硅基板或SOI基板，这取决于电路布局的整体组态与集成电路150的效能。此外，硅基半导体层102通常可设于基板101“上面”，其中半导体层102可包含极大量的电路组件，例如晶体管、电容器、电阻器及其类似者，如集成电路150想要的功能特性所要求者。如前述，持续缩小电路组件的关键尺寸导致量产技术所生产的目前市售精密半导体器件中之晶体管的关键尺寸有50纳米及更小的数量级。半导体芯片100包含金属化系统110，亦即在先进器件的器件层(device level)中，其包含多个金属化层，其中金属线路及导通孔埋入适当的电介质材料。如上述，用于各种金属化层的对应电介质材料的至少一部份经常由机械稳定性有减少的材料组成以便减少邻近金属线路的寄生电容。
如先前所述，支柱结构170可装设成为金属化系统110的一部份，其中在系统110的最后一个金属化层中形成对应的铜支柱。另一方面，封装基板180包含经适当定位及制作尺寸的接触垫(未图示)用来与对应支柱或形成于其上的任何焊料接触，以便在施加热及/或机械压力后可建立各自的机械及电气连线。此外，封装基板180通常包含适当的传导线路以便连接支柱结构170的上支柱部份与对应端子，然后建立至其它周边组件(例如印刷线路板及其类似者)的电气接口。为求便于说明，不图示任何此类传导线路。
在集成电路150的操作期间，在半导体芯片100内会产生热，例如由形成于半导体层102中及上面之电路组件产生的热。取决于基板101的整体导热性，例如用金属化系统110及支柱结构170以高度有效的方式及/或经由基板101来耗散此废热。例如，由于使半导体层102与其余基板材料隔开的埋藏绝缘氧化物层的导热性减少，SOI基板的散热能力明显小于纯硅基板。因此，由支柱结构170及封装基板180来提供主要的散热路径。结果，在半导体芯片100以及封装基板180会产生中高的平均温度，其中，如前述，这两个组件的热膨胀系数失配可能产生显着的机械应力。以箭头103及183所示的举例说明，相较于半导体芯片100，封装基板180有增加的热膨胀，其中对应失配因此产生程度明显的热应力，特别是在半导体芯片100与封装基板180的“接口”处，亦即，尤其在集成电路150的操作期间，支柱结构170与金属化系统110可能经历由热失配产生的显着剪切力(shearforce)。由于精密电介质材料的机械稳定性及黏着性减少，可能出现对应的缺陷，这会影响集成电路150的整体可靠性。特别是，支柱结构170之个别支柱的刚性可能导致局部的高剪切力而转移到金属化系统，不过，在局部极受限的区域中，会导致脱层(delamination)缺陷及其类似者。
图1b示意图示一部份集成电路150以便图解说明在封装基板180与半导体芯片100之间出现显着热失配的情形。如图示，一部份金属化系统110可图示成其中之最后金属化层140可包含埋入接触垫141的电介质材料142，而在精密应用系统中，接触垫141可包含铜材料。此外，也被称作最终钝化层的钝化层160设于最后金属化层140上以及暴露一部份的接触垫141。此外，金属支柱171(例如，铜支柱)可由最终钝化层160延伸至封装基板180，亦即形成于其中的对应接触垫181。此外，通常焊料173可形成于金属支柱171上以及可连接至接触垫181。此外，如虚线所示，形成于最终钝化层160的开口经常可小于金属支柱171的宽度171w，从而形成连接金属支柱171与接触垫141的接触区172。结果，在操作期间，剪切力183、103在金属支柱171底部与最终钝化层160接触处，特别是在对应部份165处，可产生一定的扭矩。结果，在此区域，最大机械应力可以局部选择性的方式作用于金属化系统110，从而促成主要源于区域165的对应缺陷。
结果，尽管芯片、封装基板之间基于铜支柱的先进接触方案可以减少的必要占地面积方式提供关于散热能力及导电率的显着优点，从而允许增强接触组件的密度及/或用于散热的虚拟组件(dummyelements)，产生于金属化系统110的增加机械应力可能与精密半导体器件的可靠性要求不一致。因此之故，常常会减少铜支柱的高度，不过，这伴随对应地减少封装基板与芯片的间隔，接着这可能导致任何填底材料(underfill material)的不可靠填入。因此，填底材料的对应空穴也可能造成高度的不可靠性，例如由导热率及其类似者的不均匀性造成的。在其它的习知方法中，可基于较不敏感的低介电常数电介质材料或超低介电常数材料来形成金属化系统以便增强金属化系统的机械稳定性，不过这会伴随电气效能因寄生电容增加而显着降低，导致讯号传播延迟增加。
鉴于上述情形，本揭示内容是有关于数种方法及半导体器件，其中可装设支柱结构同时避免或至少减少上述问题中的一个或更多的影响。
发明内容
本揭示内容大体有关于数种半导体器件及制造技术，其中通过减少在金属支柱与最终钝化层接触处的最大力，可减少机械应力经由支柱结构转移至金属化系统的负面影响，同时仍在金属支柱的顶面保持必要的接触面积。为此目的，在本文揭示的一些图解说明态样中，可选择金属支柱在其顶面的横向尺寸以符合连接至封装基板的要求，同时在另一方面，可大幅减少金属支柱在其底部的横向尺寸(亦即，在对应至最终钝化层表面的高度处)，从而也减少转移至金属化系统的“点状”应力。结果，可提供呈钉状组态的金属支柱，这可通过适当地修改金属沉积的制程来实现，但不会明显增加整体制程的复杂度。
揭示于本文的一个例示半导体器件包含形成于基板上面及包含最终钝化层的金属化系统。此外，该半导体器件包含由该最终钝化层伸出的金属支柱，其中该金属支柱与形成于该金属化系统的接触垫接触。此外，该金属支柱在该最终钝化层处有第一横向尺寸以及在其正面有第二横向尺寸，其中该第一横向尺寸小于该第二横向尺寸。
揭示于本文的一个例示方法包含下列步骤：在半导体器件的金属化系统的最终钝化层上面形成第一沉积掩膜，其中该第一沉积掩膜有具第一宽度的第一开口。另外，该方法包含下列步骤：在该第一沉积掩膜上面形成第二沉积掩膜，其中该第二沉积掩膜有具大于第一宽度的第二宽度且与该第一开口对齐的第二开口。最后，该方法包含下列步骤：使用该第一及第二沉积掩膜来形成金属支柱。
揭示于本文的另一例示方法是有关于形成半导体器件。该方法包含下列步骤：在多个金属化层上面形成最终钝化层以及在该最终钝化层中形成开口以便暴露接触垫的一部份。另外，该方法包含下列步骤：形成金属支柱以便由该最终钝化层伸出，其中该金属支柱在该最终钝化层的顶面有第一横向尺寸以及在其顶面有第二横向尺寸，其中相对于该第二横向尺寸，该第一横向尺寸至少比该第二横向尺寸少百分之30。
附图说明
本揭示内容的其它具体实施例定义于随附权利要求书，由以下参考附图的详细说明可更加明白这些具体实施例。
图1a及图1b的横截面图示意图示集成电路包含用有习知组态的支柱结构连接从而产生高机械应力的半导体芯片与封装基板；以及
图2a至图2e的横截面图根据示范具体实施例示意图示半导体器件包含精密金属化系统及有金属支柱的支柱结构，该金属支柱有“钉状”组态用以减少金属化系统的最大应力分量同时仍然考虑到至封装基板的必要连接。
具体实施方式
尽管用如以下详细说明及附图所图解说明的具体实施例来描述本揭示内容，然而应了解，以下详细说明及附图并非旨限制本揭示内容为所揭示的特定示范具体实施例，而是所描述的具体实施例只是用来举例说明揭示于本文之专利标的各种方面，其范畴是由随附定义权利要求书。
一般而言，本揭示内容提供半导体器件及技术可有效利用包含金属支柱之精密金属化系统而不会过度增加金属化系统的局部应力负载，从而提供使用高度精密电介质材料的可能性，如先前所述，这些电介质材料有低于习知电介质的机械稳定性。对于与提供用于连接至封装基板之接触面积有关的给定要求，可通过减少作用于最终钝化层的扭力而有效降低局部应力负载或力，这可通过适当地减少金属支柱中与最终钝化层接触之区域的横向尺寸或宽度或直径同时至少在金属支柱正面提供想要的较大宽度来实现。结果，可减少金属支柱与最终钝化层之电介质材料的接口的现有扭力，从而也减少任何底层材料(例如，敏感低介电常数电介质材料)的局部负载，藉此增强在用于连接半导体芯片与封装基板的制程期间以及也在集成电路操作期间的整体稳定性，如上述。在本文的一些具体实施例中，金属支柱可选定减少的横向尺寸或宽度使得此横向尺寸也实质对应至连接金属支柱与最后金属化层之接触垫之连接区的横向尺寸，然而在其它情形下，该连接区可基于想要的直径形成，接着是金属支柱的下半部有较大的宽度，不过，它与习知支柱结构相比显着减少，接着是金属支柱的上半部有要求的较大横向尺寸以便符合连接及其类似者的要求。
请参考图2a至图2e，此时更详细地描述其它的示范具体实施例，其中若合适，也可参考图1a至图1b。
图2a的横截面图示意图示处于进一步制造阶段的半导体器件200。如图示，依照组件200的整体组态所要求的，半导体器件200可包含基板201，例如硅基板、SOI基板及其类似者。此外，器件层或半导体层202可形成于基板201上面以及可包含大量的电路组件，例如晶体管、电容器、电阻器及其类似者，这可基于对应至器件200的适当设计规则来形成。例如，器件层202中之电路组件的关键尺寸可为约50纳米及更小，从而也需要精密金属化系统。应了解，尽管本文所揭示的技术在复杂半导体器件的背景下是高度有利的，用于形成支柱结构的对应方案也可有利地应用于较不关键的半导体器件，其中电路组件可具有50纳米及更大的关键尺寸。此外，半导体器件200可包含金属化系统210，通常它包含多个金属化层220、…、240，在一些示范具体实施例中，其中至少有一些包含敏感电介质材料，如前述。此外，最后金属化层240可能已在其中形成形式为接触垫241的金属区域，它可由任何适当材料构成，例如铜、铝、铜/铝及其类似者。应了解，在精密金属化系统中，因为铜在热及电气导电率方面有优异的特性，可基于铜材料来设置金属线路及导通孔，如前述。不过，应注意，也可考虑包含其它材料(例如铝、银及其类似者，这些可能与其它金属结合)的金属化系统。此外，如有必要，接触垫241可包含任何适当阻障材料以便在认为金属与周遭电介质材料242直接接触为不适当的时候，可靠地局限对应金属(例如，铜)。
此外，最终钝化层260可形成于最后金属化层240上面以及可包含两个或更多子层261、262，依照与钝化、机械完整性及其类似者有关的整体特性所要求者。例如，第一子层261可由二氧化硅、氮化硅及其类似者构成，而第二子层262可为钝化作用材料，例如聚酰胺及其类似者。在图示的制造阶段中，开口263可形成于最终钝化层260以便延伸至接触垫241，其中可根据公认有效的加工策略来选定开口263的对应横向尺寸及最终钝化层260的厚度，使得最终钝化层260及开口263的对应特性兼容于用以形成支柱于最终钝化层260上面的习知策略。在其它情形下，若需要，可选择小于习知设计策略的开口宽度。此外，可提供第一沉积掩膜264以便定义金属支柱中将会基于掩膜264来形成之第一部份的位置及横向尺寸。为此目的，沉积掩膜264可包含有经适当选定之横向尺寸或宽度264w的开口264a，对于其它相同的组件要求，横向尺寸或宽度264w可显着小于习知金属支柱。例如，对应习知横向尺寸用虚线264c表示。例如，习知宽度264c可实质对应至连接至封装基板所需的所欲横截面面积，如先前所述。例如，如果需要直径约100至30微米的接触面积，亦即会选定约100至30微米的习知宽度264c，相对于仍待形成的金属支柱之接触面之要求尺寸的横向尺寸，开口264a可选定约有百分之70或更小的宽度264w，例如百分之50或更小。此外，沉积掩膜264的厚度264t可经选定成对应至金属支柱中有减少横向尺寸之部份的所欲高度。例如，厚度264t可对应至仍待形成的金属支柱之大约一半的最终高度，然而在其它情形下，若需要，可选择经进一步减少的厚度。
如图2a所示的半导体器件200可基于以下的加工策略来形成，首先，器件层202以及包含金属化层220、230及240的金属化系统210中的电路组件可基于任何适当的加工策略来形成，其中，若需要，可维持所欲技术标准及加工技术的高度兼容性。之后，例如通过沉积对应电介质材料，例如子层261、262，随后用公认有效的微影技术来图样化它们，可形成最终钝化层260。例如，可提供形式为感光材料的聚亚酰胺材料262以及用对应显影制程进行图样化，接着是蚀刻层261。在其它情形下，可提供对应的抗蚀剂掩膜(resist mask)以蚀刻穿过最终钝化层260以便暴露部份接触垫241。如有必要，若是认为与钝化层260之材料直接接触不适当的话，可沉积任何适当阻障材料265以便局限对应的反应金属，例如铜。此外，鉴于待形成于开口263中及于最终钝化层260的顶面260s及侧壁260w之暴露部份上的金属有增强的黏着性，层265可能有利。为此目的，可使用任何适当材料，例如铬、铜、钽、氮化钽及其类似者，或各种材料的组合。之后，可提供例如形式为抗蚀剂材料的沉积掩膜264，其中可选择它的厚度以便得到想要的目标厚度264t。在一些示范具体实施例中，在提供掩膜材料后，可进行平坦化制程以便得到所欲目标厚度264t。之后，用适当微影掩膜可图样化开口264a以便得到减少的宽度264w。
图2b示意图示处于更进一步制造阶段的半导体器件200。如图示，第二沉积掩膜266可形成于沉积掩膜264上面而且其中已形成与开口264a及263对齐的开口266a，它可定义金属支柱中仍待基于开口264a、266a来形成之部份的横向位置与大小及形状。结果，可选定宽度266w及开口266a的整体形状以便符合让金属支柱连接至封装基板的要求，也如在说明图1a及图1b之集成电路150时所述。结果，在一些具体实施例中，如果考虑高度精密应用系统的话，宽度266w可在100至30微米之间，或者甚至更小。由于相较于尺寸264w，尺寸266w显着增加，所以待基于开口266a、264a来形成的金属支柱可具有“钉状”组态，以便减少作用于最终钝化层260的局部扭力。此外，可提供有任何适当厚度的沉积掩膜266以便容纳仍待形成(如有必要，可能结合其它的材料，例如焊料及其类似者)之金属支柱的上半部之厚度。可提供形式为抗蚀剂材料的沉积掩膜，它的图样化可取决于加工策略而使用公认有效的微影技术，亦即通过提供正性抗蚀剂或负性抗蚀剂，以及移除抗蚀剂材料的暴露部份或非暴露部份。之后，如有必要，可进行湿化学清洗制程以预备接触垫241的暴露表面，它可能结合对应阻障材料(未图示)，如在解释图2a时提及的阻障材料265。
图2c示意图示暴露于沉积环境205的半导体器件200，此时可填入适当的金属材料于开口266a、264a内以便形成金属支柱271。应了解，在图示于图2a至图2c的具体实施例中，在沉积制程205期间也可形成连接件272于开口263内，藉此基于相同的材料可形成连接件272以及包含尺寸由开口264a定义之下半部271l和尺寸由开口266a定义之上半部271u的金属支柱271。在其它情形下，若认为适当，可分开形成连接部份272与金属支柱271。例如，基于最终钝化层260及开口263，可用电化学沉积技术沉积特定材料，之后，可形成第一及第二沉积掩膜264及266以便基于特定金属材料来提供有所欲组态的金属支柱271。
沉积制程205可包含任何适当电化学沉积技术，例如无电镀法(electroless plating)、电镀法及其类似者，其中在一些具体实施例中，可使用无电镀法技术而不需要在完成金属支柱271后必须予以图样化的对应电流分布层(current distribution layer)。为此目的，可使用多个公认有效的沉积处方。在一些具体实施例中，如有必要，例如考虑到增强在用以在稍后制造阶段直接连接至封装基板之接触垫及其类似者之对应制程期间的效能，可形成附加帽盖材料(capmaterial)于顶面271s上。
图2d根据其它的示范具体实施例示意图示半导体器件200，其中在沉积制程206(例如，电化学沉积制程)期间可沉积例如形式为焊料(例如，无铅焊料)的另一材料273，因此可使用公认有效的沉积处方。为此目的，可适当地选定沉积掩膜266的厚度以便容纳金属支柱271(亦即它的上半部271u)以及材料273的所欲厚度。之后，沉积掩膜266及264可用任何适当蚀刻技术移除，例如电浆剥离法及其类似者，接着是任何其它蚀刻制程以便移除部份电流分布层，若有的话，阻障材料及其类似者。应了解，如果此种材料有必要从最终钝化层260中被移除，可使用适当的各向同性蚀刻处方(isotropic etch recipe)，使得上半部271u的阴影效应(shadowing effect)不会负面影响任何材料的有效移除。
图2e根据一些示范具体实施例示意图示处于更进一步制造阶段的半导体器件200。如图示，器件200可包含金属支柱271，其包括各自有可依上述方式选定之横向尺寸266w、264w的上半部271u及下半部271l。此外，在图示具体实施例中，形式为焊料的附加材料273可形成于金属支柱271上面，以及在图示具体实施例中，有在回焊先前所沉积之焊料后得到的增强形状。在其它具体实施例中，如图2c所示，可提供没有附加焊料的金属支柱271，或如图2d所示，若有的话，可省略焊料273的回焊。如图示，在一些具体实施例中，可选定减少的横向尺寸264w使得金属支柱271中至少一部份可“停留”在最终钝化层260上面，如部份271r所示。就此情形而言，由于有整体减少的宽度264w，可减少作用于最终钝化层260表面的对应机械力，如先前所述。结果，也可减少作用于位在最终钝化层260下面之任何材料的对应局部机械应力，从而减少产生缺陷的机率，例如脱层、破裂及其类似者。在其它的示范具体实施例中，可选定尺寸264w以便实质对应至连接件272的横向尺寸263w，从而也减少作用于最终钝化层260在局部发生所得到的力。又在其它的示范具体实施例中，可选定小于尺寸263w的横向尺寸264w，如271d所示，从而实质完全避免金属支柱271与钝化层260的表面260s的相互作用。应了解，通过适当地选择沉积掩膜264的开口264a的宽度(参考图2b)，可实现横向宽度264w的对应改变。
结果，本揭示内容提供半导体器件及制造技术，其中通过减少金属支柱下半部的横向尺寸，可减少在钝化材料表面与金属支柱之间的接口处的局部力，同时上半部可维持用以连接至封装基板的想要的表面积。结果，相较于习知焊料，可使用刚性提高的任何想要的材料，例如铜、铜合金、镍及其类似者，同时也提供精密电介质材料使用于金属化系统的可能性而不必妥协金属支柱结构的整体连接性。
熟谙此艺者基于本说明可明白本揭示内容的其它修改及变体。因此，本说明应被视为仅供图解说明而且目的是用来教导熟谙此艺者实施本文所揭示之原理的一般方式。应了解，应将图示及描述于本文的形式应视为目前为较佳的具体实施例。

Claims (25)

1.一种半导体器件，包含：
形成于基板上面的金属化系统，该金属化系统包含最终钝化层；以及
由该最终钝化层伸出的金属支柱，该金属支柱与形成于该金属化系统的接触垫接触以及在该最终钝化层有第一横向尺寸，以及在该金属支柱的顶面有第二横向尺寸，该第一横向尺寸小于该第二横向尺寸。
2.如权利要求1所述的半导体器件，还包括该最终钝化层中的开口，其中该开口填满连接该金属支柱与该接触垫的接触金属。
3.如权利要求2所述的半导体器件，其中该开口的横向尺寸实质上等于该第一横向尺寸。
4.如权利要求2所述的半导体器件，其中该开口的该横向尺寸小于该第一横向尺寸。
5.如权利要求2所述的半导体器件，其中该接触金属与该金属支柱由相同的含金属材料构成。
6.如权利要求1所述的半导体器件，还包含形成于该金属支柱的该顶面上面的焊料。
7.如权利要求6所述的半导体器件，其中提供该焊料作为回焊焊料。
8.如权利要求1所述的半导体器件，其中该金属支柱包含铜。
9.如权利要求1所述的半导体器件，其中该金属支柱的该第二横向尺寸大约有30至100微米。
10.如权利要求1所述的半导体器件，其中该第一横向尺寸的数值大约为该第二横向尺寸的百分之50或更小。
11.一种方法，其包含下列步骤：
在半导体器件的金属化系统的最终钝化层上面形成第一沉积掩膜，该第一沉积掩膜有具第一宽度的第一开口；
在该第一沉积掩膜上面形成第二沉积掩膜，该第二沉积掩膜有与该第一开口对齐的第二开口，该第二开口有大于该第一宽度的第二宽度；以及
用该第一及第二沉积掩膜形成金属支柱。
12.如权利要求11所述的方法，其中形成该第一及第二沉积掩膜的步骤包含下列步骤：形成第一抗蚀剂掩膜及在该第一抗蚀剂掩膜上形成第二抗蚀剂掩膜。
13.如权利要求11所述的方法，还包含下列步骤：在该最终钝化层中形成开口，其中该最终钝化层的该开口有小于该第二宽度的宽度。
14.如权利要求13所述的方法，其中该最终钝化层的该开口的宽度小于该第一宽度。
15.如权利要求11所述的方法，还包含下列步骤：在该金属支柱的顶面上面形成焊料。
16.如权利要求15所述的方法，还包含下列步骤：在使该半导体器件连接至封装基板之前，回焊该焊料。
17.如权利要求11所述的方法，其中该第二宽度大约等于100微米或更小。
18.一种形成半导体器件的方法，该方法包含下列步骤：
在多个金属化层上面形成最终钝化层；
在该最终钝化层中形成开口以便暴露接触垫的一部份；以及
形成由该最终钝化层伸出的金属支柱，该金属支柱在该最终钝化层的顶面有第一横向尺寸，该金属支柱在其顶面还有第二横向尺寸，相对于该第二横向尺寸，该第一横向尺寸至少比该第二横向尺寸少百分之30。
19.如权利要求18所述的方法，其中该第一横向尺寸至少少百分之50。
20.如权利要求18所述的方法，其中形成该金属支柱包含下列步骤：在该最终钝化层上面形成第一沉积掩膜以及在该第一沉积掩膜上面形成第二沉积掩膜，其中该第一沉积掩膜有与该最终钝化层的该开口对齐的第一开口，以及该第二沉积掩膜有与该第一开口对齐的第二开口。
21.如权利要求20所述的方法，其中该第一及第二沉积掩膜被提供作为抗蚀剂掩膜。
22.如权利要求20所述的方法，其中在一共同沉积制程中将金属材料填入该第一及第二开口与该最终钝化层的该开口以便形成该金属支柱以及连接该金属支柱与该接触垫的连接件。
23.如权利要求18所述的方法，其中该金属支柱由含铜材料形成。
24.如权利要求18所述的方法，还包含下列步骤：在该金属支柱的该顶面上面形成焊料。
25.如权利要求24所述的方法，其中基于共同沉积掩膜来形成该焊料及该金属支柱。
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