JP2012515432A - シリコン貫通電極(tsv)を露出させ接触させる高歩留まりの方法 - Google Patents
シリコン貫通電極(tsv)を露出させ接触させる高歩留まりの方法 Download PDFInfo
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Abstract
【解決手段】 前側および裏側を有する本体を有する主ウェハを含むアセンブリを取得する。主ウェハは、裏側より上で終端する複数のブラインド電気バイアを有する。ブラインド電気バイアは、導電コアを有し、コアの隣接する側方領域および端部領域に周囲絶縁体を有する。ハンドラ・ウェハは、主ウェハの本体の前側に固定されている。追加のステップは、裏側でブラインド電気バイアを露出させることを含む。ブラインド電気バイアは、裏側全体で様々な高さに露出される。別のステップは、裏側に第1の化学機械研磨プロセスを適用して、露出ステップの後に残っているコアの端部領域に隣接した周囲絶縁体を開放すると共に、バイア導電コア、コアの側方領域に隣接した周囲絶縁体、および主ウェハの本体を同一平面にすることを含む。更に別のステップは、裏側をエッチングして、裏側全体でバイアの各々の均一なスタンドオフ高さを与えることを含む。更に、裏側全体に誘電体を堆積し、裏側に第2の化学機械研磨プロセスを適用して、バイアの導電コアに隣接した誘電体のみを開放する。
【選択図】 図9
Description
ハンドラ・ウェハのボンディングの後、ウェハ対(例えば公称約1.4mm厚さ)を市販のウェハ研削ツールに移す。機械的薄化は、例えば以下のような3つのステップを含む。すなわち、粗い研削、細かい研削、および最終研磨である。図2に示すように、最終目標深さは、約110μmの合計の深さ「Z」とし、公称100μm深さのTSV232(寸法「X」)を覆う〜10μmのシリコン(寸法「Y」)を残すように設定する。研削は、ウェハ202の裏側234上に実行する。粗い研削を用いてウェハの大部分を除去するが、粗い研削プロセスは極めて迅速であるものの、極めて粗い表面を生じ、表面の下の少なくとも〜30μmの深さまで損傷が入り込む。このため、最終目標に到達する前に少なくとも約30μmで粗い研削プロセスを停止し、次いで細かい研削ホイールに切り換えることが好ましい。細かい研削を用いて、最後の約30μm(以上)のシリコンを除去しなければならない。これによって、粗い研削によって生成された表面下の損傷が効果的に除去される。
図3から図6は、TSV露出およびフィールド絶縁ステップを示す。1つ以上の実施形態において、このシーケンスは極めて重要である。なぜなら、ここでの裏側処理が不良であると、直接的に、FBEOLメタライゼーションの間のシリコン基板中のTSV漏れにつながり、入出力(I/O)、電力、および接地接続について一様に問題が生じるからである。図3を参照すると、TSVを露出させる好適な方法は、ブランケット・ディープ反応性イオン・エッチング(D−RIE)(〜4μm/分)または適度に迅速な(〜1μm/分)Si反応性イオン・エッチング(RIE)プロセスを用いることである。均一な厚さのガラス・ハンドラを用いている場合、3分から6分後にウェハ裏側234の全体でTSVパターンが露出される。もっと時間が長くなると、シリコンの粗さが増すと共に、ウェハ縁部の近くに「ブラック・シリコン」残留物が蓄積する。エッチングによって、最初の裏面290の下の深さDまで材料が除去される。Dは、例えば約10ミクロンとすることができる。
標準的な相補型金属酸化膜半導体(CMOS)ウェハにおいて典型的であるように、最終端子金属または「ウェハ・バンプ形成」プロセスは、適切なアンダーバンプ・メタライゼーション(UBM)・パッドおよびC4(Controlled Collapse Chip Connection)はんだバンプをウェハ全体に堆積することを含む。UBMのための典型的なプロセスは、金属スパッタリングの後にリソグラフィ、電解めっき、およびウェット・シード・エッチングを行ってパッドを画定することを含む。また、過去においては、整列シャドー・マスクを介した金属の蒸着を用いて成功している。この結果、図8に示すように、TSVタングステン・コア238に直接接触した整列パッド250を有するウェハが得られる。DuPont RISTONフォトレジスト(RISTONはE. I. DuPont De Nemous and Company(19898デラウェア州ウィルミントン、マーケット・ストリート1007の登録商標である)等の厚いレジスト・マスクを介して、はんだバンプを直接めっきすることも可能である。または、はんだバンプは、IBM社のC4NPプロセスにおけるように、型から濡れ性のあるUBMパッドに移すことも可能である。IBM社のC4NPプロセスの態様は、米国特許第5,244,143号、第5,775,569号、および第7,332,424号において開示されている。図9に示す最終結果は、はんだバンプ260を有する薄いバンプ・シリコン・キャリア202であり、ガラス・ハンドラ230に取り付けられて、試験、ダイシング、ピック、およびアセンブリのための準備が整っている。以前の裏側プロセスと同様、UBMパッドおよびはんだバンプを製造するためにどの方法を選ぶ場合であっても、ガラスが裏に取り付けられたウェハに対応するためにはツール類を適切に選択しなければならない。当業者は、本明細書における教示が与えられれば、適切なツール類を容易に選択することができる。
Claims (19)
- アセンブリであって、
前側および裏側を有する本体を有する主ウェハであって、前記主ウェハが前記裏側より上で終端する複数のブラインド電気バイアを含み、前記ブラインド電気バイアが導電コアを有し、前記コアの隣接する側方領域および端部領域に周囲絶縁体を有する、前記主ウェハと、
前記前側に固定されたハンドラ・ウェハと、
を含む前記アセンブリを取得するステップと、
前記裏側で前記ブラインド電気バイアを露出させるステップであって、前記ブラインド電気バイアが裏側全体で様々な高さに露出される、前記ステップと、
前記裏側に第1の化学機械研磨プロセスを適用して、前記露出ステップの後に残っている前記コアの前記端部領域に隣接した前記周囲絶縁体を開放すると共に、前記バイア導電コア、前記コアの前記側方領域に隣接した前記周囲絶縁体、および前記主ウェハの前記本体を同一平面にするステップと、
前記裏側をエッチングして、前記裏側全体で前記バイアの各々の均一なスタンドオフ高さを与える、ステップと、
前記裏側全体に誘電体を堆積するステップと、
前記裏側に第2の化学機械研磨プロセスを適用して、前記バイアの前記導電コアに隣接した前記誘電体のみを開放するステップと、
を含む、方法。 - 前記アセンブリを取得する前記ステップは、
シリコンを含む前記主ウェハを取得することと、
ガラスを含む前記ハンドラ・ウェハを取得することと、
前記主ウェハを前記ハンドラ・ウェハに結合することと、
を含む、請求項1に記載の方法。 - 前記ハンドラ・ウェハは全体の厚さのばらつきが5ミクロン未満である、請求項2に記載の方法。
- 前記ブラインド電気バイアを露出させる前記ステップが、
前記ブラインド・バイアがほぼ露出するまで前記裏側から材料を除去することによって前記ウェハを薄化することと、
前記裏側をエッチングして前記バイアを前記様々な高さに露出させることと、
を含む、請求項2に記載の方法。 - 前記薄化するステップが所望の深さまで実行され、前記薄化するステップが、
前記裏側に、前記所望の深さから30ミクロン以上遠くまで粗い研削動作を実行することと、
前記所望の深さまで細かい研削動作を実行することと、
研磨動作を実行することと、
を含む、請求項4に記載の方法。 - 前記裏側をエッチングして前記バイアを前記様々な高さに露出させる前記ステップがディープ反応性イオン・エッチングを含む、請求項4に記載の方法。
- 前記ディープ反応性イオン・エッチングが毎分4ミクロンで実行される、請求項6に記載の方法。
- 前記裏側をエッチングして前記バイアを前記様々な高さに露出させる前記ステップがシリコン反応性イオン・エッチングを含む、請求項4に記載の方法。
- 前記シリコン反応性イオン・エッチングが毎分1ミクロンで実行される、請求項8に記載の方法。
- 前記様々な高さが3ミクロンから8ミクロンの範囲である、請求項4に記載の方法。
- 前記誘電体の前記堆積がプラズマ増強化学気相堆積によって実行される、請求項4に記載の方法。
- 前記誘電体の前記堆積によって前記バイアの上にキャップが生成され、前記第2の化学機械的研磨プロセスによって前記キャップが除去される、請求項4に記載の方法。
- 前記裏側で前記複数のバイアの前記導電コアの上に複数の導電パッド構造を形成する追加ステップを更に含む、請求項4に記載の方法。
- 前記導電パッド構造がアンダーバンプ・メタライゼーション・パッドを含む、請求項13に記載の方法。
- 前記アンダーバンプ・メタライゼーション・パッド上にC4はんだバンプを形成することを更に含む、請求項14に記載の方法。
- 前記バイアの断面がスロット状である、請求項4に記載の方法。
- 前記バイアの断面がバー状である、請求項4に記載の方法。
- 前記バイアの断面が環状である、請求項4に記載の方法。
- 前記バイアの断面がC型である、請求項4に記載の方法。
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US12/352,718 US8263497B2 (en) | 2009-01-13 | 2009-01-13 | High-yield method of exposing and contacting through-silicon vias |
PCT/EP2010/050155 WO2010081767A1 (en) | 2009-01-13 | 2010-01-08 | High-yield method of exposing and contacting through-silicon vias |
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JP2014033159A (ja) * | 2012-08-06 | 2014-02-20 | Disco Abrasive Syst Ltd | ウエーハの加工方法 |
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JP5662947B2 (ja) | 2015-02-04 |
KR20110106915A (ko) | 2011-09-29 |
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US20100178766A1 (en) | 2010-07-15 |
EP2345070B1 (en) | 2012-03-21 |
US8263497B2 (en) | 2012-09-11 |
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