JP2012512497A5 - - Google Patents

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Publication number
JP2012512497A5
JP2012512497A5 JP2011542283A JP2011542283A JP2012512497A5 JP 2012512497 A5 JP2012512497 A5 JP 2012512497A5 JP 2011542283 A JP2011542283 A JP 2011542283A JP 2011542283 A JP2011542283 A JP 2011542283A JP 2012512497 A5 JP2012512497 A5 JP 2012512497A5
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JP
Japan
Prior art keywords
voltage
delay
circuit
paths
path
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Application number
JP2011542283A
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English (en)
Japanese (ja)
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JP2012512497A (ja
JP5355711B2 (ja
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Priority claimed from US12/336,741 external-priority patent/US7876631B2/en
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Publication of JP2012512497A publication Critical patent/JP2012512497A/ja
Publication of JP2012512497A5 publication Critical patent/JP2012512497A5/ja
Application granted granted Critical
Publication of JP5355711B2 publication Critical patent/JP5355711B2/ja
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JP2011542283A 2008-12-17 2009-12-11 複数の電圧領域を使用した回路内信号経路遅延の自己同調 Active JP5355711B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/336,741 US7876631B2 (en) 2008-12-17 2008-12-17 Self-tuning of signal path delay in circuit employing multiple voltage domains
US12/336,741 2008-12-17
PCT/US2009/067657 WO2010077776A1 (en) 2008-12-17 2009-12-11 Self-tuning of signal path delay in circuit employing multiple voltage domains

Publications (3)

Publication Number Publication Date
JP2012512497A JP2012512497A (ja) 2012-05-31
JP2012512497A5 true JP2012512497A5 (enExample) 2013-06-27
JP5355711B2 JP5355711B2 (ja) 2013-11-27

Family

ID=41559655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011542283A Active JP5355711B2 (ja) 2008-12-17 2009-12-11 複数の電圧領域を使用した回路内信号経路遅延の自己同調

Country Status (7)

Country Link
US (1) US7876631B2 (enExample)
EP (1) EP2380174B1 (enExample)
JP (1) JP5355711B2 (enExample)
KR (1) KR101259899B1 (enExample)
CN (1) CN102246236B (enExample)
TW (1) TWI427640B (enExample)
WO (1) WO2010077776A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8930733B2 (en) * 2009-06-12 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Separating power domains of central processing units
US8995207B2 (en) 2011-08-12 2015-03-31 Qualcomm Incorporated Data storage for voltage domain crossings
US20130227197A1 (en) * 2012-02-29 2013-08-29 Sandisk Technologies Inc. Multiple pre-driver logic for io high speed interfaces
US8638153B2 (en) * 2012-03-29 2014-01-28 Qualcomm Incorporated Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width
CN102723755A (zh) * 2012-06-14 2012-10-10 北京华大智宝电子系统有限公司 一种电池组信息采集管理结构
US9070433B1 (en) 2014-03-11 2015-06-30 International Business Machines Corporation SRAM supply voltage global bitline precharge pulse
US9418716B1 (en) * 2015-04-15 2016-08-16 Qualcomm Incorporated Word line and bit line tracking across diverse power domains
CN104868906A (zh) * 2015-05-26 2015-08-26 施文斌 集成电路和电压选择电路
US9954527B2 (en) * 2015-09-29 2018-04-24 Nvidia Corporation Balanced charge-recycling repeater link
KR102531863B1 (ko) * 2018-03-28 2023-05-11 삼성전자주식회사 반도체 메모리 장치의 홀드-마진을 제어하는 방법 및 시스템

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04362810A (ja) * 1991-06-11 1992-12-15 Fuji Electric Co Ltd 論理信号遅延回路
JPH10284705A (ja) 1997-04-10 1998-10-23 Hitachi Ltd ダイナミック型ｒａｍ
US6034920A (en) * 1998-11-24 2000-03-07 Texas Instruments Incorporated Semiconductor memory device having a back gate voltage controlled delay circuit
JP2002109887A (ja) * 2000-09-29 2002-04-12 Hitachi Ltd 半導体集積回路
JP3908493B2 (ja) * 2001-08-30 2007-04-25 株式会社東芝 電子回路及び半導体記憶装置
JP3866594B2 (ja) * 2002-03-15 2007-01-10 Ｎｅｃエレクトロニクス株式会社 遅延回路と半導体記憶装置及び半導体記憶装置の制御方法
US6831853B2 (en) * 2002-11-19 2004-12-14 Taiwan Semiconductor Manufacturing Company Apparatus for cleaning a substrate
US7073145B2 (en) * 2003-01-07 2006-07-04 International Business Machines Corporation Programmable delay method for hierarchical signal balancing
KR20060056360A (ko) * 2003-08-04 2006-05-24 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 전력 공급 구조물 및 이의 설계 방법
US7151396B2 (en) 2005-04-04 2006-12-19 Freescale Semiconductor, Inc. Clock delay compensation circuit
US7355905B2 (en) * 2005-07-01 2008-04-08 P.A. Semi, Inc. Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage
KR100655084B1 (ko) * 2006-01-17 2006-12-08 삼성전자주식회사 센스앰프 인에이블 회로 및 이를 갖는 반도체 메모리 장치
US7542331B1 (en) * 2007-10-16 2009-06-02 Juhan Kim Planar SRAM including segment read circuit
US7388774B1 (en) * 2007-10-16 2008-06-17 Juhan Kim SRAM including bottom gate transistor
US7542348B1 (en) * 2007-12-19 2009-06-02 Juhan Kim NOR flash memory including bipolar segment read circuit

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