CN102246236B - 使用多个电压域的电路中的信号路径延迟的自调谐 - Google Patents
使用多个电压域的电路中的信号路径延迟的自调谐 Download PDFInfo
- Publication number
- CN102246236B CN102246236B CN200980150177.7A CN200980150177A CN102246236B CN 102246236 B CN102246236 B CN 102246236B CN 200980150177 A CN200980150177 A CN 200980150177A CN 102246236 B CN102246236 B CN 102246236B
- Authority
- CN
- China
- Prior art keywords
- voltage
- delay
- path
- circuit
- paths
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/336,741 | 2008-12-17 | ||
| US12/336,741 US7876631B2 (en) | 2008-12-17 | 2008-12-17 | Self-tuning of signal path delay in circuit employing multiple voltage domains |
| PCT/US2009/067657 WO2010077776A1 (en) | 2008-12-17 | 2009-12-11 | Self-tuning of signal path delay in circuit employing multiple voltage domains |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102246236A CN102246236A (zh) | 2011-11-16 |
| CN102246236B true CN102246236B (zh) | 2014-09-03 |
Family
ID=41559655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200980150177.7A Active CN102246236B (zh) | 2008-12-17 | 2009-12-11 | 使用多个电压域的电路中的信号路径延迟的自调谐 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7876631B2 (enExample) |
| EP (1) | EP2380174B1 (enExample) |
| JP (1) | JP5355711B2 (enExample) |
| KR (1) | KR101259899B1 (enExample) |
| CN (1) | CN102246236B (enExample) |
| TW (1) | TWI427640B (enExample) |
| WO (1) | WO2010077776A1 (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8930733B2 (en) * | 2009-06-12 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Separating power domains of central processing units |
| US8995207B2 (en) | 2011-08-12 | 2015-03-31 | Qualcomm Incorporated | Data storage for voltage domain crossings |
| US20130227197A1 (en) * | 2012-02-29 | 2013-08-29 | Sandisk Technologies Inc. | Multiple pre-driver logic for io high speed interfaces |
| US8638153B2 (en) | 2012-03-29 | 2014-01-28 | Qualcomm Incorporated | Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width |
| CN102723755A (zh) * | 2012-06-14 | 2012-10-10 | 北京华大智宝电子系统有限公司 | 一种电池组信息采集管理结构 |
| US9070433B1 (en) | 2014-03-11 | 2015-06-30 | International Business Machines Corporation | SRAM supply voltage global bitline precharge pulse |
| US9418716B1 (en) * | 2015-04-15 | 2016-08-16 | Qualcomm Incorporated | Word line and bit line tracking across diverse power domains |
| CN104868906A (zh) * | 2015-05-26 | 2015-08-26 | 施文斌 | 集成电路和电压选择电路 |
| US9954527B2 (en) * | 2015-09-29 | 2018-04-24 | Nvidia Corporation | Balanced charge-recycling repeater link |
| KR102531863B1 (ko) * | 2018-03-28 | 2023-05-11 | 삼성전자주식회사 | 반도체 메모리 장치의 홀드-마진을 제어하는 방법 및 시스템 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6031779A (en) * | 1997-04-10 | 2000-02-29 | Hitachi, Ltd. | Dynamic memory |
| US20060220721A1 (en) * | 2005-04-04 | 2006-10-05 | Nitin Vig | Clock delay compensation circuit |
| CN101004945A (zh) * | 2006-01-17 | 2007-07-25 | 三星电子株式会社 | 用于使能感应放大器的电路以及具有其的半导体存储器件 |
| US20080056031A1 (en) * | 2002-03-15 | 2008-03-06 | Nec Electronics Corporation | Semiconductor memory |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04362810A (ja) * | 1991-06-11 | 1992-12-15 | Fuji Electric Co Ltd | 論理信号遅延回路 |
| US6034920A (en) * | 1998-11-24 | 2000-03-07 | Texas Instruments Incorporated | Semiconductor memory device having a back gate voltage controlled delay circuit |
| JP2002109887A (ja) * | 2000-09-29 | 2002-04-12 | Hitachi Ltd | 半導体集積回路 |
| JP3908493B2 (ja) * | 2001-08-30 | 2007-04-25 | 株式会社東芝 | 電子回路及び半導体記憶装置 |
| US6831853B2 (en) * | 2002-11-19 | 2004-12-14 | Taiwan Semiconductor Manufacturing Company | Apparatus for cleaning a substrate |
| US7073145B2 (en) * | 2003-01-07 | 2006-07-04 | International Business Machines Corporation | Programmable delay method for hierarchical signal balancing |
| KR20060056360A (ko) * | 2003-08-04 | 2006-05-24 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | 전력 공급 구조물 및 이의 설계 방법 |
| US7355905B2 (en) * | 2005-07-01 | 2008-04-08 | P.A. Semi, Inc. | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage |
| US7542332B1 (en) * | 2007-10-16 | 2009-06-02 | Juhan Kim | Stacked SRAM including segment read circuit |
| US7388774B1 (en) * | 2007-10-16 | 2008-06-17 | Juhan Kim | SRAM including bottom gate transistor |
| US7542348B1 (en) * | 2007-12-19 | 2009-06-02 | Juhan Kim | NOR flash memory including bipolar segment read circuit |
-
2008
- 2008-12-17 US US12/336,741 patent/US7876631B2/en active Active
-
2009
- 2009-12-11 WO PCT/US2009/067657 patent/WO2010077776A1/en not_active Ceased
- 2009-12-11 JP JP2011542283A patent/JP5355711B2/ja active Active
- 2009-12-11 KR KR1020117016788A patent/KR101259899B1/ko active Active
- 2009-12-11 EP EP09793663.7A patent/EP2380174B1/en active Active
- 2009-12-11 CN CN200980150177.7A patent/CN102246236B/zh active Active
- 2009-12-17 TW TW098143418A patent/TWI427640B/zh active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6031779A (en) * | 1997-04-10 | 2000-02-29 | Hitachi, Ltd. | Dynamic memory |
| US20080056031A1 (en) * | 2002-03-15 | 2008-03-06 | Nec Electronics Corporation | Semiconductor memory |
| US20060220721A1 (en) * | 2005-04-04 | 2006-10-05 | Nitin Vig | Clock delay compensation circuit |
| CN101004945A (zh) * | 2006-01-17 | 2007-07-25 | 三星电子株式会社 | 用于使能感应放大器的电路以及具有其的半导体存储器件 |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI427640B (zh) | 2014-02-21 |
| WO2010077776A1 (en) | 2010-07-08 |
| KR101259899B1 (ko) | 2013-05-02 |
| TW201040984A (en) | 2010-11-16 |
| BRPI0922986A2 (pt) | 2016-01-26 |
| US7876631B2 (en) | 2011-01-25 |
| KR20110106386A (ko) | 2011-09-28 |
| CN102246236A (zh) | 2011-11-16 |
| US20100148839A1 (en) | 2010-06-17 |
| JP2012512497A (ja) | 2012-05-31 |
| JP5355711B2 (ja) | 2013-11-27 |
| EP2380174A1 (en) | 2011-10-26 |
| EP2380174B1 (en) | 2016-03-23 |
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| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |