TWI427640B - 使用多電壓域之電路中信號路徑延遲之自調整 - Google Patents
使用多電壓域之電路中信號路徑延遲之自調整 Download PDFInfo
- Publication number
- TWI427640B TWI427640B TW098143418A TW98143418A TWI427640B TW I427640 B TWI427640 B TW I427640B TW 098143418 A TW098143418 A TW 098143418A TW 98143418 A TW98143418 A TW 98143418A TW I427640 B TWI427640 B TW I427640B
- Authority
- TW
- Taiwan
- Prior art keywords
- voltage
- delay
- circuit
- path
- paths
- Prior art date
Links
- 239000000872 buffer Substances 0.000 claims description 42
- 230000003111 delayed effect Effects 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 20
- 230000004044 response Effects 0.000 claims description 14
- 230000001413 cellular effect Effects 0.000 claims description 3
- 230000001934 delay Effects 0.000 claims description 3
- 230000008859 change Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000003068 static effect Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000013500 data storage Methods 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000006249 magnetic particle Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 238000013341 scale-up Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000010977 unit operation Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/336,741 US7876631B2 (en) | 2008-12-17 | 2008-12-17 | Self-tuning of signal path delay in circuit employing multiple voltage domains |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201040984A TW201040984A (en) | 2010-11-16 |
| TWI427640B true TWI427640B (zh) | 2014-02-21 |
Family
ID=41559655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW098143418A TWI427640B (zh) | 2008-12-17 | 2009-12-17 | 使用多電壓域之電路中信號路徑延遲之自調整 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7876631B2 (enExample) |
| EP (1) | EP2380174B1 (enExample) |
| JP (1) | JP5355711B2 (enExample) |
| KR (1) | KR101259899B1 (enExample) |
| CN (1) | CN102246236B (enExample) |
| TW (1) | TWI427640B (enExample) |
| WO (1) | WO2010077776A1 (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8930733B2 (en) * | 2009-06-12 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Separating power domains of central processing units |
| US8995207B2 (en) | 2011-08-12 | 2015-03-31 | Qualcomm Incorporated | Data storage for voltage domain crossings |
| US20130227197A1 (en) * | 2012-02-29 | 2013-08-29 | Sandisk Technologies Inc. | Multiple pre-driver logic for io high speed interfaces |
| US8638153B2 (en) | 2012-03-29 | 2014-01-28 | Qualcomm Incorporated | Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width |
| CN102723755A (zh) * | 2012-06-14 | 2012-10-10 | 北京华大智宝电子系统有限公司 | 一种电池组信息采集管理结构 |
| US9070433B1 (en) | 2014-03-11 | 2015-06-30 | International Business Machines Corporation | SRAM supply voltage global bitline precharge pulse |
| US9418716B1 (en) * | 2015-04-15 | 2016-08-16 | Qualcomm Incorporated | Word line and bit line tracking across diverse power domains |
| CN104868906A (zh) * | 2015-05-26 | 2015-08-26 | 施文斌 | 集成电路和电压选择电路 |
| US9954527B2 (en) * | 2015-09-29 | 2018-04-24 | Nvidia Corporation | Balanced charge-recycling repeater link |
| KR102531863B1 (ko) * | 2018-03-28 | 2023-05-11 | 삼성전자주식회사 | 반도체 메모리 장치의 홀드-마진을 제어하는 방법 및 시스템 |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6031779A (en) * | 1997-04-10 | 2000-02-29 | Hitachi, Ltd. | Dynamic memory |
| US6034920A (en) * | 1998-11-24 | 2000-03-07 | Texas Instruments Incorporated | Semiconductor memory device having a back gate voltage controlled delay circuit |
| US20040133864A1 (en) * | 2003-01-07 | 2004-07-08 | International Business Machines Corporation | Programmable delay method for hierarchical signal balancing |
| US20060214696A1 (en) * | 2003-08-04 | 2006-09-28 | Daniel Timmermans | Voltage supply structure and method |
| US20060220721A1 (en) * | 2005-04-04 | 2006-10-05 | Nitin Vig | Clock delay compensation circuit |
| US20080056031A1 (en) * | 2002-03-15 | 2008-03-06 | Nec Electronics Corporation | Semiconductor memory |
| US7388774B1 (en) * | 2007-10-16 | 2008-06-17 | Juhan Kim | SRAM including bottom gate transistor |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04362810A (ja) * | 1991-06-11 | 1992-12-15 | Fuji Electric Co Ltd | 論理信号遅延回路 |
| JP2002109887A (ja) * | 2000-09-29 | 2002-04-12 | Hitachi Ltd | 半導体集積回路 |
| JP3908493B2 (ja) * | 2001-08-30 | 2007-04-25 | 株式会社東芝 | 電子回路及び半導体記憶装置 |
| US6831853B2 (en) * | 2002-11-19 | 2004-12-14 | Taiwan Semiconductor Manufacturing Company | Apparatus for cleaning a substrate |
| US7355905B2 (en) * | 2005-07-01 | 2008-04-08 | P.A. Semi, Inc. | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage |
| KR100655084B1 (ko) * | 2006-01-17 | 2006-12-08 | 삼성전자주식회사 | 센스앰프 인에이블 회로 및 이를 갖는 반도체 메모리 장치 |
| US7542332B1 (en) * | 2007-10-16 | 2009-06-02 | Juhan Kim | Stacked SRAM including segment read circuit |
| US7542348B1 (en) * | 2007-12-19 | 2009-06-02 | Juhan Kim | NOR flash memory including bipolar segment read circuit |
-
2008
- 2008-12-17 US US12/336,741 patent/US7876631B2/en active Active
-
2009
- 2009-12-11 WO PCT/US2009/067657 patent/WO2010077776A1/en not_active Ceased
- 2009-12-11 JP JP2011542283A patent/JP5355711B2/ja active Active
- 2009-12-11 KR KR1020117016788A patent/KR101259899B1/ko active Active
- 2009-12-11 EP EP09793663.7A patent/EP2380174B1/en active Active
- 2009-12-11 CN CN200980150177.7A patent/CN102246236B/zh active Active
- 2009-12-17 TW TW098143418A patent/TWI427640B/zh active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6031779A (en) * | 1997-04-10 | 2000-02-29 | Hitachi, Ltd. | Dynamic memory |
| US6034920A (en) * | 1998-11-24 | 2000-03-07 | Texas Instruments Incorporated | Semiconductor memory device having a back gate voltage controlled delay circuit |
| US20080056031A1 (en) * | 2002-03-15 | 2008-03-06 | Nec Electronics Corporation | Semiconductor memory |
| US20040133864A1 (en) * | 2003-01-07 | 2004-07-08 | International Business Machines Corporation | Programmable delay method for hierarchical signal balancing |
| US20060214696A1 (en) * | 2003-08-04 | 2006-09-28 | Daniel Timmermans | Voltage supply structure and method |
| US20060220721A1 (en) * | 2005-04-04 | 2006-10-05 | Nitin Vig | Clock delay compensation circuit |
| US7388774B1 (en) * | 2007-10-16 | 2008-06-17 | Juhan Kim | SRAM including bottom gate transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2010077776A1 (en) | 2010-07-08 |
| CN102246236B (zh) | 2014-09-03 |
| KR101259899B1 (ko) | 2013-05-02 |
| TW201040984A (en) | 2010-11-16 |
| BRPI0922986A2 (pt) | 2016-01-26 |
| US7876631B2 (en) | 2011-01-25 |
| KR20110106386A (ko) | 2011-09-28 |
| CN102246236A (zh) | 2011-11-16 |
| US20100148839A1 (en) | 2010-06-17 |
| JP2012512497A (ja) | 2012-05-31 |
| JP5355711B2 (ja) | 2013-11-27 |
| EP2380174A1 (en) | 2011-10-26 |
| EP2380174B1 (en) | 2016-03-23 |
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