JP2012503321A5 - - Google Patents

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Publication number
JP2012503321A5
JP2012503321A5 JP2011527336A JP2011527336A JP2012503321A5 JP 2012503321 A5 JP2012503321 A5 JP 2012503321A5 JP 2011527336 A JP2011527336 A JP 2011527336A JP 2011527336 A JP2011527336 A JP 2011527336A JP 2012503321 A5 JP2012503321 A5 JP 2012503321A5
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JP
Japan
Prior art keywords
intermetallic layer
layer
solder material
intermetallic
conductive material
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Application number
JP2011527336A
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English (en)
Japanese (ja)
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JP5438114B2 (ja
JP2012503321A (ja
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Priority claimed from PCT/EP2009/062125 external-priority patent/WO2010031845A1/en
Publication of JP2012503321A publication Critical patent/JP2012503321A/ja
Publication of JP2012503321A5 publication Critical patent/JP2012503321A5/ja
Application granted granted Critical
Publication of JP5438114B2 publication Critical patent/JP5438114B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2011527336A 2008-09-18 2009-09-18 材料ボンディングのための方法およびシステム Active JP5438114B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US9819408P 2008-09-18 2008-09-18
US61/098,194 2008-09-18
PCT/EP2009/062125 WO2010031845A1 (en) 2008-09-18 2009-09-18 Methods and systems for material bonding

Publications (3)

Publication Number Publication Date
JP2012503321A JP2012503321A (ja) 2012-02-02
JP2012503321A5 true JP2012503321A5 (https=) 2012-06-21
JP5438114B2 JP5438114B2 (ja) 2014-03-12

Family

ID=41268461

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011527336A Active JP5438114B2 (ja) 2008-09-18 2009-09-18 材料ボンディングのための方法およびシステム

Country Status (4)

Country Link
US (1) US8536047B2 (https=)
EP (1) EP2340554B1 (https=)
JP (1) JP5438114B2 (https=)
WO (1) WO2010031845A1 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2363373A1 (en) * 2010-03-02 2011-09-07 SensoNor Technologies AS Bonding process for sensitive micro-and nano-systems
EP2654075B1 (de) * 2010-03-31 2016-09-28 EV Group E. Thallner GmbH Verfahren zum permanenten Verbinden zweier Metalloberflächen
US8802553B2 (en) 2011-02-10 2014-08-12 Infineon Technologies Ag Method for mounting a semiconductor chip on a carrier
JP5588419B2 (ja) * 2011-10-26 2014-09-10 株式会社東芝 パッケージ
US8916448B2 (en) 2013-01-09 2014-12-23 International Business Machines Corporation Metal to metal bonding for stacked (3D) integrated circuits
US9802360B2 (en) 2013-06-04 2017-10-31 Stratsys, Inc. Platen planarizing process for additive manufacturing system
DE102014116030A1 (de) * 2014-11-04 2016-05-04 Infineon Technologies Ag Verfahren zur Herstellung einer Verbindung und Anordnung für eine Chipzusammenstellung mit Direktverbindung
CN105826243A (zh) * 2015-01-09 2016-08-03 中芯国际集成电路制造(上海)有限公司 晶圆键合方法以及晶圆键合结构
US9620434B1 (en) 2016-03-07 2017-04-11 Toyota Motor Engineering & Manufacturing North America, Inc. High temperature bonding processes incorporating metal particles and bonded substrates formed therefrom
JP2017204599A (ja) * 2016-05-13 2017-11-16 日本電気硝子株式会社 気密パッケージの製造方法及び気密パッケージ
EP3754706A1 (en) 2019-06-20 2020-12-23 IMEC vzw A method for the electrical bonding of semiconductor components
US11164845B2 (en) 2020-01-30 2021-11-02 International Business Machines Corporation Resist structure for forming bumps
JP7590931B2 (ja) * 2021-06-16 2024-11-27 ルネサスエレクトロニクス株式会社 半導体装置
US20230036201A1 (en) * 2021-07-30 2023-02-02 Stmicroelectronics, Inc. Leadless semiconductor package with de-metallized porous structures and method for manufacturing the same
US20250140657A1 (en) * 2023-10-27 2025-05-01 Ideal Semiconductor Devices, Inc. Semiconductor device and method of fabricating same

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US27294A (en) * 1860-02-28 Henry isham
US114662A (en) * 1871-05-09 Improvement in iron culverts
US3839727A (en) * 1973-06-25 1974-10-01 Ibm Semiconductor chip to substrate solder bond using a locally dispersed, ternary intermetallic compound
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WO2001086715A2 (de) * 2000-05-05 2001-11-15 Infineon Technologies Ag Verfahren zum verlöten einer ersten metallschicht, die eine dicke von weniger als 5 $g(m)m aufweist, mit einer zweiten metallschicht, löteinrichtung und halbleiterchip-montagevorrichtung
US6492197B1 (en) * 2000-05-23 2002-12-10 Unitive Electronics Inc. Trilayer/bilayer solder bumps and fabrication methods therefor
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JP3682654B2 (ja) * 2002-09-25 2005-08-10 千住金属工業株式会社 無電解Ｎｉメッキ部分へのはんだ付け用はんだ合金
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JP5535448B2 (ja) * 2008-05-19 2014-07-02 シャープ株式会社 半導体装置、半導体装置の実装方法、および半導体装置の実装構造

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