JP2012059885A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
- Publication number
- JP2012059885A JP2012059885A JP2010201025A JP2010201025A JP2012059885A JP 2012059885 A JP2012059885 A JP 2012059885A JP 2010201025 A JP2010201025 A JP 2010201025A JP 2010201025 A JP2010201025 A JP 2010201025A JP 2012059885 A JP2012059885 A JP 2012059885A
- Authority
- JP
- Japan
- Prior art keywords
- island
- fixing member
- semiconductor device
- mold
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
【解決手段】アイランド21,31が形成されたリードフレーム20,30を用意し、アイランド21,31の他側面21b,31bに固定部材50を固定し、アイランド21,31の一側面21a,31aにパワー素子11,12を実装し、固定部材50およびパワー素子11,12が取り付けられたアイランド21,31を金型70内に配置して、型締時にこの金型70に設けられる押圧部(73,74)により露出面50aが金型70の内壁面72aに面接触するように固定部材50を内壁面72aに向けて押圧し、金型70内にモールド樹脂60を構成する封止用材料を注入して固定部材50の露出面50aが露出するように半導体素子およびアイランドを封止する。
【選択図】図4
Description
したがって、半導体素子を実装したアイランドに固定される固定部材の露出面でのバリの発生を防止して、当該露出面を封止部材から確実に露出させることができる。
なお、第2工程において、他側面への固定部材の固定と一側面への半導体素子の実装とは、どちらを先に実施してもよいが、他側面への固定部材の固定を先に実施する方が、半導体素子の実装時にアイランドが固定部材に固定されているため、半導体素子に関する電気的接続作業が容易になる。
以下、本発明の半導体装置の製造方法を具現化した第1実施形態について、図面を参照して説明する。図1は、第1実施形態に係る半導体装置10の構成を概略的に示す断面図である。図2は、図1の両アイランド21,31と固定部材50との接着固定状態を示す説明図である。
したがって、パワー素子11,12等の半導体素子を実装したアイランド21,31に固定される固定部材50の露出面50aでのバリの発生を防止して、当該露出面50aをモールド樹脂60から確実に露出させることができる。
次に、本発明の第2実施形態に係る半導体装置について図16を参照して説明する。図16は、第2実施形態に係る半導体装置10の要部を示す一部断面図である。
図16に示すように、本第2実施形態に係る半導体装置10は、リードフレーム20,30に代えてリードフレーム20e,30eを採用する点が、上記第1実施形態および各変形例に係る半導体装置と異なる。したがって、第1実施形態の半導体装置と実質的に同一の構成部分には、同一符号を付し、その説明を省略する。
次に、本発明の第3実施形態に係る半導体装置について図17を参照して説明する。図17は、第3実施形態に係る半導体装置10の要部を示す一部断面図である。
図17に示すように、本第3実施形態に係る半導体装置10は、金型70に代えて金型70aを採用する点が、上記第1実施形態および各変形例に係る半導体装置と異なる。したがって、第1実施形態の半導体装置と実質的に同一の構成部分には、同一符号を付し、その説明を省略する。
(1)上述した固定部材50を内壁面72aに向けて押圧する押圧部として、金型70の押圧用ピン73のみを採用してもよいし、挟持部74のみを採用してもよい。また、上記押圧部として、押圧用ピン73および挟持部74に加えて、固定部材50を内壁面72aに向けて押圧するための他の部材を採用してもよい。
11,12…パワー素子(半導体素子)
13…制御IC
19a,19b…リードフレーム(接触部)
20,20a〜20e,30,30d,30e,40…リードフレーム
21,24a,24b,31,41…アイランド
22,26a,32,36a…外側端部(被挟持部)
50…固定部材
50a…露出面
50b…非固定部
51…絶縁シート(絶縁部材)
52…銅箔(放熱部材)
60…モールド樹脂(封止部材)
70,70a…金型
71…上型
72…下型
72a…内壁面
73…押圧用ピン(押圧部)
74…挟持部(押圧部)
75…凸部
Claims (16)
- リードフレームのアイランドの一側面に半導体素子が実装されるとともに他側面に固定部材が固定され、この固定部材の露出面が露出するように前記半導体素子および前記アイランドが封止部材により封止される半導体装置の製造方法であって、
前記アイランドが形成された前記リードフレームを用意する第1工程と、
前記アイランドの前記他側面に前記固定部材を固定するとともに前記アイランドの前記一側面に前記半導体素子を実装する第2工程と、
前記固定部材および前記半導体素子が取り付けられた前記アイランドを金型内に配置して、型締時にこの金型に設けられる押圧部により前記露出面が前記金型の内壁面に面接触するように前記固定部材を前記内壁面に向けて押圧する第3工程と、
前記金型内に前記封止部材を構成する封止用材料を注入して前記固定部材の前記露出面が露出するように前記半導体素子および前記アイランドを封止する第4工程と、
を備えることを特徴とする半導体装置の製造方法。 - 前記押圧部は、前記金型に複数個所設けられることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記リードフレームには、複数のアイランドが形成されており、
前記第2工程では、前記複数のアイランドのそれぞれの前記他側面に共通の前記固定部材を固定することを特徴とする請求項1または2に記載の半導体装置の製造方法。 - 前記第2工程では、前記半導体素子が前記アイランドの前記一側面に実装された後に、当該半導体素子と前記封止部材により封止される他の素子とを電気的に接続することを特徴とする請求項1〜3のいずれか一項に記載の半導体装置の製造方法。
- 前記第2工程では、前記半導体素子が前記アイランドの前記一側面に実装された後に、当該半導体素子と前記封止部材により封止される他の素子とをワイヤボンディングにより電気的に接続することを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記固定部材は、絶縁部材に放熱部材の一側面を貼り付けて構成され、前記放熱部材の他側面が前記露出面として前記封止部材から露出することを特徴とする請求項1〜5のいずれか一項に記載の半導体装置の製造方法。
- 前記絶縁部材は、接着性を有する絶縁シートであることを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記押圧部は、前記金型に取り付けられる押圧用ピンであって、
前記第3工程では、前記押圧用ピンにより、前記固定部材のうち前記アイランドが固定される固定部と異なる非固定部が前記内壁面に向けて押圧されることを特徴とする請求項1〜7のいずれか一項に記載の半導体装置の製造方法。 - 前記リードフレームには、前記アイランドと異なる部位であって、前記押圧用ピンと前記非固定部との双方に押圧状態で接触する接触部が設けられることを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記押圧部は、前記金型の分割面に形成されて型締時に前記リードフレームの被挟持部を挟持する挟持部であって、
前記リードフレームは、前記被挟持部が前記挟持部により挟持されるとき、当該リードフレームの弾性力により前記アイランドに固定される前記固定部材の前記露出面が前記内壁面に押圧されるように形成されることを特徴とする請求項1〜7のいずれか一項に記載の半導体装置の製造方法。 - 前記リードフレームは、前記被挟持部が前記挟持部により挟持されるとき、当該リードフレームの弾性力により前記アイランドに固定される前記固定部材の前記露出面が前記内壁面に押圧されるように、前記アイランドが前記被挟持部から離間するほど前記内壁面に近接して形成されることを特徴とする請求項10に記載の半導体装置の製造方法。
- 前記押圧部は、前記挟持部と前記金型に取り付けられる押圧用ピンとであって、
前記第3工程では、前記押圧用ピンにより、前記固定部材のうち前記アイランドが固定される固定部と異なる非固定部が前記内壁面に向けて押圧されることを特徴とする請求項10または11に記載の半導体装置の製造方法。 - 前記第3工程では、前記押圧用ピンにより、前記非固定部のうち前記被挟持部から離れた部位が前記内壁面に向けて押圧されることを特徴とする請求項12に記載の半導体装置の製造方法。
- 前記金型には、前記封止用材料が注入される注入口と前記内壁面との間であって当該内壁面の近傍に凸部が形成されることを特徴とする請求項1〜13のいずれか一項に記載の半導体装置の製造方法。
- リードフレームのアイランドの一側面に半導体素子が実装されるとともに他側面に固定部材が固定され、この固定部材の露出面が露出するように前記半導体素子および前記アイランドが封止部材により封止される半導体装置であって、
前記リードフレームには、前記アイランドと異なる部位であって、封止用の金型による型締時に当該金型の押圧部と前記固定部材のうち前記露出面とは反対側の面との双方に押圧状態で接触する接触部が設けられることを特徴とする半導体装置。 - 前記接触部は、前記固定部材の前記反対側の面にのうち外縁近傍にて押圧状態で接触するように形成されることを特徴とする請求項15に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010201025A JP5598189B2 (ja) | 2010-09-08 | 2010-09-08 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010201025A JP5598189B2 (ja) | 2010-09-08 | 2010-09-08 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012059885A true JP2012059885A (ja) | 2012-03-22 |
JP5598189B2 JP5598189B2 (ja) | 2014-10-01 |
Family
ID=46056636
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010201025A Expired - Fee Related JP5598189B2 (ja) | 2010-09-08 | 2010-09-08 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5598189B2 (ja) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014041852A (ja) * | 2012-08-21 | 2014-03-06 | Mitsubishi Electric Corp | パワーモジュール |
JP2014072304A (ja) * | 2012-09-28 | 2014-04-21 | Sanken Electric Co Ltd | 半導体モジュールの製造方法、半導体モジュール |
JP2015037103A (ja) * | 2013-08-12 | 2015-02-23 | 新電元工業株式会社 | 半導体装置及び半導体装置の製造方法 |
WO2015173862A1 (ja) * | 2014-05-12 | 2015-11-19 | 三菱電機株式会社 | 電力用半導体装置及びその製造方法 |
JPWO2015145752A1 (ja) * | 2014-03-28 | 2017-04-13 | 三菱電機株式会社 | 半導体モジュールおよび半導体モジュールを搭載した駆動装置 |
NL2021929A (en) * | 2017-11-10 | 2019-05-15 | Shindengen Electric Mfg | Electronic module and method of manufacturing the same |
WO2022224904A1 (ja) * | 2021-04-21 | 2022-10-27 | 三菱電機株式会社 | 半導体装置およびその製造方法ならびに電力変換装置 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05291459A (ja) * | 1992-04-07 | 1993-11-05 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JPH0758245A (ja) * | 1993-08-12 | 1995-03-03 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2005109100A (ja) * | 2003-09-30 | 2005-04-21 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2008112924A (ja) * | 2006-10-31 | 2008-05-15 | Denso Corp | 半導体装置の製造方法 |
JP2008141140A (ja) * | 2006-12-05 | 2008-06-19 | Denso Corp | 半導体装置 |
JP2010140930A (ja) * | 2008-12-09 | 2010-06-24 | Denso Corp | モールドパッケージの製造方法 |
-
2010
- 2010-09-08 JP JP2010201025A patent/JP5598189B2/ja not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05291459A (ja) * | 1992-04-07 | 1993-11-05 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JPH0758245A (ja) * | 1993-08-12 | 1995-03-03 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2005109100A (ja) * | 2003-09-30 | 2005-04-21 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2008112924A (ja) * | 2006-10-31 | 2008-05-15 | Denso Corp | 半導体装置の製造方法 |
JP2008141140A (ja) * | 2006-12-05 | 2008-06-19 | Denso Corp | 半導体装置 |
JP2010140930A (ja) * | 2008-12-09 | 2010-06-24 | Denso Corp | モールドパッケージの製造方法 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014041852A (ja) * | 2012-08-21 | 2014-03-06 | Mitsubishi Electric Corp | パワーモジュール |
JP2014072304A (ja) * | 2012-09-28 | 2014-04-21 | Sanken Electric Co Ltd | 半導体モジュールの製造方法、半導体モジュール |
JP2015037103A (ja) * | 2013-08-12 | 2015-02-23 | 新電元工業株式会社 | 半導体装置及び半導体装置の製造方法 |
JPWO2015145752A1 (ja) * | 2014-03-28 | 2017-04-13 | 三菱電機株式会社 | 半導体モジュールおよび半導体モジュールを搭載した駆動装置 |
WO2015173862A1 (ja) * | 2014-05-12 | 2015-11-19 | 三菱電機株式会社 | 電力用半導体装置及びその製造方法 |
JPWO2015173862A1 (ja) * | 2014-05-12 | 2017-04-20 | 三菱電機株式会社 | 電力用半導体装置及びその製造方法 |
NL2021929A (en) * | 2017-11-10 | 2019-05-15 | Shindengen Electric Mfg | Electronic module and method of manufacturing the same |
US11227816B2 (en) | 2017-11-10 | 2022-01-18 | Shindengen Electric Manufacturing Co., Ltd. | Electronic module with press hole to expose surface of a conductor |
WO2022224904A1 (ja) * | 2021-04-21 | 2022-10-27 | 三菱電機株式会社 | 半導体装置およびその製造方法ならびに電力変換装置 |
JP7483128B2 (ja) | 2021-04-21 | 2024-05-14 | 三菱電機株式会社 | 半導体装置およびその製造方法ならびに電力変換装置 |
Also Published As
Publication number | Publication date |
---|---|
JP5598189B2 (ja) | 2014-10-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5598189B2 (ja) | 半導体装置の製造方法 | |
US8987877B2 (en) | Semiconductor device | |
US8188583B2 (en) | Semiconductor device and method of manufacturing same | |
JP5956783B2 (ja) | 半導体装置の製造方法 | |
JP4614107B2 (ja) | 半導体装置 | |
KR20190005736A (ko) | 반도체 모듈 | |
JP6603169B2 (ja) | 半導体装置の製造方法および半導体装置 | |
WO2012124239A1 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP4732138B2 (ja) | 半導体装置及びその製造方法 | |
JP2016201447A (ja) | モールドパッケージ | |
US20160133539A1 (en) | Mold package and manufacturing method thereof | |
JP6567957B2 (ja) | パワー半導体モジュールの製造方法 | |
JP5458476B2 (ja) | モールドパッケージおよびその製造方法 | |
JP5119092B2 (ja) | 半導体装置の製造方法 | |
JP2008258541A (ja) | 半導体装置及びその製造方法 | |
US20220301990A1 (en) | Semiconductor device | |
JP5385438B2 (ja) | 半導体装置 | |
US20220301991A1 (en) | Semiconductor device | |
JP2008218703A (ja) | 半導体装置及びその製造方法 | |
JP2000286379A (ja) | 半導体装置及びその製造方法 | |
JP2007294637A (ja) | 半導体装置の製造方法 | |
JP2012023204A (ja) | 半導体装置およびその製造方法 | |
JP2007281380A (ja) | 半導体素子およびその製造方法 | |
JP2007324394A (ja) | モールドパッケージおよびその製造方法 | |
JP2012186370A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120919 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130517 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130521 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130703 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140318 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140429 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140715 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140728 |
|
LAPS | Cancellation because of no payment of annual fees |