JP2012053555A - 半導体メモリカード及びその製造方法 - Google Patents

半導体メモリカード及びその製造方法 Download PDF

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Publication number
JP2012053555A
JP2012053555A JP2010194090A JP2010194090A JP2012053555A JP 2012053555 A JP2012053555 A JP 2012053555A JP 2010194090 A JP2010194090 A JP 2010194090A JP 2010194090 A JP2010194090 A JP 2010194090A JP 2012053555 A JP2012053555 A JP 2012053555A
Authority
JP
Japan
Prior art keywords
card
memory card
semiconductor memory
terminal
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010194090A
Other languages
English (en)
Japanese (ja)
Inventor
Taku Nishiyama
拓 西山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2010194090A priority Critical patent/JP2012053555A/ja
Priority to TW100108390A priority patent/TWI604586B/zh
Priority to CN201110066778.9A priority patent/CN102386162B/zh
Publication of JP2012053555A publication Critical patent/JP2012053555A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Credit Cards Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2010194090A 2010-08-31 2010-08-31 半導体メモリカード及びその製造方法 Pending JP2012053555A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2010194090A JP2012053555A (ja) 2010-08-31 2010-08-31 半導体メモリカード及びその製造方法
TW100108390A TWI604586B (zh) 2010-08-31 2011-03-11 Semiconductor memory card and its manufacturing method
CN201110066778.9A CN102386162B (zh) 2010-08-31 2011-03-18 半导体存储卡及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010194090A JP2012053555A (ja) 2010-08-31 2010-08-31 半導体メモリカード及びその製造方法

Publications (1)

Publication Number Publication Date
JP2012053555A true JP2012053555A (ja) 2012-03-15

Family

ID=45825427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010194090A Pending JP2012053555A (ja) 2010-08-31 2010-08-31 半導体メモリカード及びその製造方法

Country Status (3)

Country Link
JP (1) JP2012053555A (zh)
CN (1) CN102386162B (zh)
TW (1) TWI604586B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6253607B2 (ja) * 2015-03-16 2017-12-27 東芝メモリ株式会社 半導体メモリカードの製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080169541A1 (en) * 2001-09-19 2008-07-17 Jeffrey Alan Miks Enhanced durability multimedia card
JP3866178B2 (ja) * 2002-10-08 2007-01-10 株式会社ルネサステクノロジ Ｉｃカード
CN100552937C (zh) * 2006-03-31 2009-10-21 株式会社东芝 半导体器件及使用它的存储卡
US7928010B2 (en) * 2006-10-20 2011-04-19 Sandisk Corporation Method for producing portable memory devices

Also Published As

Publication number Publication date
TW201209979A (en) 2012-03-01
CN102386162B (zh) 2014-11-12
CN102386162A (zh) 2012-03-21
TWI604586B (zh) 2017-11-01

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