JP2011505589A - 選択的領域堆積と組み合わせて着色マスクを使用する方法 - Google Patents

選択的領域堆積と組み合わせて着色マスクを使用する方法 Download PDF

Info

Publication number
JP2011505589A
JP2011505589A JP2010534945A JP2010534945A JP2011505589A JP 2011505589 A JP2011505589 A JP 2011505589A JP 2010534945 A JP2010534945 A JP 2010534945A JP 2010534945 A JP2010534945 A JP 2010534945A JP 2011505589 A JP2011505589 A JP 2011505589A
Authority
JP
Japan
Prior art keywords
layer
deposition
mask
color
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010534945A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011505589A5 (enExample
Inventor
マリー アービング，リン
キャロル フリーマン，ダイアン
ジェローム カウデリー−コーバン，ピーター
ヤン，チェン
ハワード レビー，デイビッド
Original Assignee
イーストマン コダック カンパニー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by イーストマン コダック カンパニー filed Critical イーストマン コダック カンパニー
Publication of JP2011505589A publication Critical patent/JP2011505589A/ja
Publication of JP2011505589A5 publication Critical patent/JP2011505589A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0005—Production of optical devices or components in so far as characterised by the lithographic processes or materials used therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0241—Manufacture or treatment of multiple TFTs using liquid deposition, e.g. printing

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Thin Film Transistor (AREA)
  • Optical Filters (AREA)
JP2010534945A 2007-11-20 2008-11-12 選択的領域堆積と組み合わせて着色マスクを使用する方法 Pending JP2011505589A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/986,169 US8129098B2 (en) 2007-11-20 2007-11-20 Colored mask combined with selective area deposition
PCT/US2008/012762 WO2009067162A1 (en) 2007-11-20 2008-11-12 Process using colored mask combined with selective area deposition

Publications (2)

Publication Number Publication Date
JP2011505589A true JP2011505589A (ja) 2011-02-24
JP2011505589A5 JP2011505589A5 (enExample) 2013-01-24

Family

ID=40447758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010534945A Pending JP2011505589A (ja) 2007-11-20 2008-11-12 選択的領域堆積と組み合わせて着色マスクを使用する方法

Country Status (5)

Country Link
US (1) US8129098B2 (enExample)
EP (1) EP2217969A1 (enExample)
JP (1) JP2011505589A (enExample)
CN (1) CN101868761A (enExample)
WO (1) WO2009067162A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020008969A1 (ja) * 2018-07-05 2020-01-09 東レ株式会社 樹脂組成物、遮光膜、遮光膜の製造方法および隔壁付き基板
JP2021512207A (ja) * 2018-01-22 2021-05-13 メルク パテント ゲゼルシャフト ミット ベシュレンクテル ハフツングＭｅｒｃｋ Ｐａｔｅｎｔ Ｇｅｓｅｌｌｓｃｈａｆｔ ｍｉｔ ｂｅｓｃｈｒａｅｎｋｔｅｒ Ｈａｆｔｕｎｇ 誘電材料
WO2024194943A1 (ja) * 2023-03-17 2024-09-26 株式会社レゾナック 感光性樹脂組成物、感光性エレメント、レジストパターンの形成方法及び配線基板の製造方法
WO2024194942A1 (ja) * 2023-03-17 2024-09-26 株式会社レゾナック 感光性樹脂組成物、感光性エレメント、レジストパターンの形成方法及び配線基板の製造方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8221964B2 (en) * 2007-11-20 2012-07-17 Eastman Kodak Company Integrated color mask
DE102008054219A1 (de) * 2008-10-31 2010-05-06 Osram Opto Semiconductors Gmbh Organisches strahlungsemittierendes Bauelement und Verfahren zur Herstellung eines organischen strahlungsemittierenden Bauelements
KR101044279B1 (ko) * 2009-07-30 2011-06-28 서강대학교산학협력단 Ｃｍｐ 연마패드와 그의 제조방법
TWI449007B (zh) 2011-09-16 2014-08-11 E Ink Holdings Inc 可撓性顯示裝置的製造方法
US8791023B2 (en) * 2012-08-31 2014-07-29 Eastman Kodak Company Patterned thin film dielectric layer formation
US8927434B2 (en) * 2012-08-31 2015-01-06 Eastman Kodak Company Patterned thin film dielectric stack formation
CN105511227B (zh) * 2015-12-26 2019-08-02 杭州福斯特应用材料股份有限公司 一种具有良好孔掩蔽功能的干膜抗蚀剂及其层压体
CN106298070B (zh) * 2016-08-29 2017-09-15 上海交通大学 一种图形化导电薄膜的制备方法
CN108020991A (zh) * 2016-10-31 2018-05-11 无锡中微掩模电子有限公司 集成电路用掩模版背曝方法
CN108063089B (zh) * 2016-11-08 2020-07-17 中国科学院微电子研究所 一种mos器件原子层沉积原位制备方法
KR20230037751A (ko) 2021-09-09 2023-03-17 삼성디스플레이 주식회사 표시 장치, 표시 장치의 제조장치 및 표시 장치의 제조방법

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5379466A (en) * 1976-12-23 1978-07-13 Ibm Method of forming negative mask
JPS54114254A (en) * 1978-01-30 1979-09-06 Eastman Kodak Co Color filter arraging structure using light fading color
JPH01235383A (ja) * 1988-03-16 1989-09-20 Matsushita Electric Ind Co Ltd 薄膜電界効果トランジスターの製造方法
JP2002026011A (ja) * 2000-07-03 2002-01-25 Nec Kagoshima Ltd パターン形成方法及び薄膜トランジスタの製造方法
JP2002082630A (ja) * 2000-05-12 2002-03-22 Semiconductor Energy Lab Co Ltd 電気光学装置
JP2004020743A (ja) * 2002-06-13 2004-01-22 Dainippon Printing Co Ltd カラーフィルタの製造方法
JP2009531848A (ja) * 2006-03-29 2009-09-03 プラスティック ロジック リミテッド 自己整合電極を有するデバイスの作製方法
JP2009537310A (ja) * 2006-05-19 2009-10-29 イーストマン コダック カンパニー 透明構造体を形成するための着色マスキング
JP2011503670A (ja) * 2007-11-20 2011-01-27 イーストマン コダック カンパニー ディスプレイ回路を製造するための多色マスク方法
JP2011503668A (ja) * 2007-11-20 2011-01-27 イーストマン コダック カンパニー 集積化カラーマスク

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4345011A (en) * 1978-01-30 1982-08-17 Eastman Kodak Company Color imaging devices and color filter arrays using photo-bleachable dyes
FR2595155B1 (fr) 1986-02-28 1988-04-29 Commissariat Energie Atomique Procede de realisation de filtres colores en bandes et d'electrodes en bandes auto-alignes pour une cellule d'affichage polychrome a film liquide et cellule correspondante
US5262893A (en) * 1991-11-04 1993-11-16 Massachusetts Institute Of Technology Method and apparatus for creating multiple phase level optical elements
US5391507A (en) * 1993-09-03 1995-02-21 General Electric Company Lift-off fabrication method for self-aligned thin film transistors
US6338988B1 (en) * 1999-09-30 2002-01-15 International Business Machines Corporation Method for fabricating self-aligned thin-film transistors to define a drain and source in a single photolithographic step
GB9927287D0 (en) * 1999-11-19 2000-01-12 Koninkl Philips Electronics Nv Top gate thin film transistor and method of producing the same
US20020159008A1 (en) * 2000-03-10 2002-10-31 Takeru Yoshino Color liquid crystal display device and method for manufacturing a color filter
US6803160B2 (en) * 2001-12-13 2004-10-12 Dupont Photomasks, Inc. Multi-tone photomask and method for manufacturing the same
US7390597B2 (en) * 2002-06-13 2008-06-24 Dai Nippon Printing Co., Ltd. Method for manufacturing color filter
US7056834B2 (en) * 2004-02-10 2006-06-06 Hewlett-Packard Development Company, L.P. Forming a plurality of thin-film devices using imprint lithography
US7259106B2 (en) * 2004-09-10 2007-08-21 Versatilis Llc Method of making a microelectronic and/or optoelectronic circuitry sheet
US7100510B2 (en) * 2005-02-09 2006-09-05 Eastman Kodak Company Method for registering patterns on a web
US7160819B2 (en) * 2005-04-25 2007-01-09 Sharp Laboratories Of America, Inc. Method to perform selective atomic layer deposition of zinc oxide
US20060267136A1 (en) * 2005-05-24 2006-11-30 International Business Machines Corporation Integrated circuit (ic) with on-chip programmable fuses
US8500985B2 (en) * 2006-07-21 2013-08-06 Novellus Systems, Inc. Photoresist-free metal deposition

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5379466A (en) * 1976-12-23 1978-07-13 Ibm Method of forming negative mask
JPS54114254A (en) * 1978-01-30 1979-09-06 Eastman Kodak Co Color filter arraging structure using light fading color
JPH01235383A (ja) * 1988-03-16 1989-09-20 Matsushita Electric Ind Co Ltd 薄膜電界効果トランジスターの製造方法
JP2002082630A (ja) * 2000-05-12 2002-03-22 Semiconductor Energy Lab Co Ltd 電気光学装置
JP2002026011A (ja) * 2000-07-03 2002-01-25 Nec Kagoshima Ltd パターン形成方法及び薄膜トランジスタの製造方法
JP2004020743A (ja) * 2002-06-13 2004-01-22 Dainippon Printing Co Ltd カラーフィルタの製造方法
JP2009531848A (ja) * 2006-03-29 2009-09-03 プラスティック ロジック リミテッド 自己整合電極を有するデバイスの作製方法
JP2009537310A (ja) * 2006-05-19 2009-10-29 イーストマン コダック カンパニー 透明構造体を形成するための着色マスキング
JP2011503670A (ja) * 2007-11-20 2011-01-27 イーストマン コダック カンパニー ディスプレイ回路を製造するための多色マスク方法
JP2011503668A (ja) * 2007-11-20 2011-01-27 イーストマン コダック カンパニー 集積化カラーマスク

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021512207A (ja) * 2018-01-22 2021-05-13 メルク パテント ゲゼルシャフト ミット ベシュレンクテル ハフツングＭｅｒｃｋ Ｐａｔｅｎｔ Ｇｅｓｅｌｌｓｃｈａｆｔ ｍｉｔ ｂｅｓｃｈｒａｅｎｋｔｅｒ Ｈａｆｔｕｎｇ 誘電材料
JP7404272B2 (ja) 2018-01-22 2023-12-25 メルク パテント ゲゼルシャフト ミット ベシュレンクテル ハフツング 誘電材料
KR102432033B1 (ko) 2018-07-05 2022-08-12 도레이 카부시키가이샤 수지 조성물, 차광막, 차광막의 제조 방법 및 격벽 구비 기판
JPWO2020008969A1 (ja) * 2018-07-05 2021-05-13 東レ株式会社 樹脂組成物、遮光膜および遮光膜の製造方法
KR20210029764A (ko) * 2018-07-05 2021-03-16 도레이 카부시키가이샤 수지 조성물, 차광막, 차광막의 제조 방법 및 격벽 구비 기판
KR20220049046A (ko) * 2018-07-05 2022-04-20 도레이 카부시키가이샤 수지 조성물, 차광막, 차광막의 제조 방법 및 격벽 구비 기판
WO2020008969A1 (ja) * 2018-07-05 2020-01-09 東レ株式会社 樹脂組成物、遮光膜、遮光膜の製造方法および隔壁付き基板
CN112368611A (zh) * 2018-07-05 2021-02-12 东丽株式会社 树脂组合物、遮光膜、遮光膜的制造方法及带隔壁的基板
KR102624898B1 (ko) 2018-07-05 2024-01-16 도레이 카부시키가이샤 수지 조성물, 차광막, 차광막의 제조 방법 및 격벽 구비 기판
WO2024194943A1 (ja) * 2023-03-17 2024-09-26 株式会社レゾナック 感光性樹脂組成物、感光性エレメント、レジストパターンの形成方法及び配線基板の製造方法
WO2024194942A1 (ja) * 2023-03-17 2024-09-26 株式会社レゾナック 感光性樹脂組成物、感光性エレメント、レジストパターンの形成方法及び配線基板の製造方法
WO2024195410A1 (ja) * 2023-03-17 2024-09-26 株式会社レゾナック 感光性樹脂組成物、感光性エレメント、レジストパターンの形成方法及び配線基板の製造方法
WO2024195502A1 (ja) * 2023-03-17 2024-09-26 株式会社レゾナック 感光性樹脂組成物、感光性エレメント、レジストパターンの形成方法及び配線基板の製造方法

Also Published As

Publication number Publication date
WO2009067162A1 (en) 2009-05-28
CN101868761A (zh) 2010-10-20
EP2217969A1 (en) 2010-08-18
US20090130609A1 (en) 2009-05-21
US8129098B2 (en) 2012-03-06

Similar Documents

Publication Publication Date Title
US8129098B2 (en) Colored mask combined with selective area deposition
JP2009537310A (ja) 透明構造体を形成するための着色マスキング
EP2256554B1 (en) Display circuitry made by multicolored mask process
US8715894B2 (en) Integrated color mask
US7846644B2 (en) Photopatternable deposition inhibitor containing siloxane
TWI493287B (zh) 顯示元件用感放射線性樹脂組成物、塗膜以及其形成方法
JP2012525000A (ja) 二重自己整合式金属酸化物薄膜トランジスタ
CN116068853A (zh) 感光性树脂组合物以及显示装置
US8173355B2 (en) Gradient colored mask
CN100592206C (zh) 用于形成图案的抗蚀剂及使用其形成图案的方法
JP2011507008A (ja) マルチカラーマスク
TW201918495A (zh) 感光性樹脂組合物
US7179697B2 (en) Method of fabricating an electronic device
CN116031308B (zh) 一种氧化物tft及其保护层的制造方法
KR102793564B1 (ko) 감방사선성 수지 조성물을 사용한 전자 장치의 제조 방법, 감방사선성 수지 조성물, 절연막 및 절연막을 구비한 전자 장치
KR101028940B1 (ko) 액정 표시 장치용 어레이 기판 및 그 제조 방법
WO2009045102A2 (en) An electronic circuit element with profiled photopatternable dielectric layer
KR20080110377A (ko) 에치레지스트 조성물 및 이를 이용한 액정표시장치의패턴형성방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111111

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20111111

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130827

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140218