JP2011501335A - Mlcnandにおける不均等閾値電圧範囲 - Google Patents
Mlcnandにおける不均等閾値電圧範囲 Download PDFInfo
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- JP2011501335A JP2011501335A JP2010528984A JP2010528984A JP2011501335A JP 2011501335 A JP2011501335 A JP 2011501335A JP 2010528984 A JP2010528984 A JP 2010528984A JP 2010528984 A JP2010528984 A JP 2010528984A JP 2011501335 A JP2011501335 A JP 2011501335A
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- 230000015654 memory Effects 0.000 claims abstract description 82
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- 238000005070 sampling Methods 0.000 description 12
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- 230000004044 response Effects 0.000 description 11
- 238000006243 chemical reaction Methods 0.000 description 9
- 238000012545 processing Methods 0.000 description 8
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
Abstract
Description
上述されたようなマルチレベルセルおよびシステムにおけるメモリセルのプログラミングのためのターゲット閾値電圧は、(時にはドメインと称される)範囲内に配置される。例えば、図6に示されるように、2ビット(4レベル)を有するMLCにおける(時にはウインドウとも称される)範囲602、604、606および608を示す一実施形態は、異なる範囲において異なるビットパターンへとプログラムされる。図6の実施形態においては、10のビットパターンは、2.5ボルトから3.5ボルトの範囲608における閾値電圧値を有し、それは典型的には範囲の中間または中間付近にある。対照的に、消去されたセル(ビットパターン11)は、−3からー2ボルトの間の範囲602内にある。
Claims (12)
- マルチレベルセルメモリをプログラムする方法であって、
各セル内に複数の閾値電圧範囲と、前記メモリセルの各レベルのための範囲とを割り当てるステップと、
前記複数の閾値電圧範囲を異なる大きさに定めるステップであって、各閾値電圧範囲はデータビットパターンを表す、ステップと、
を含む、
ことを特徴とする方法。 - 大きさを定めるステップは、レベルに対する前記閾値電圧が増加するにつれて、前記レベルによって前記複数の閾値電圧範囲の大きさを減少させるステップをさらに含む、
ことを特徴とする請求項1に記載の方法。 - 前記複数の閾値電圧範囲のうちの最大のものは、最低の閾値電圧レベルにあり、前記複数の閾値電圧範囲のうちの最小のものは、最高の閾値電圧レベルにある、
ことを特徴とする請求項1に記載の方法。 - 各範囲内の予期されたプログラムディスターブに従って、前記複数の閾値範囲を調整するステップをさらに含む、
ことを特徴とする請求項1に記載の方法。 - 調整するステップは、閾値電圧値が増加するにつれて、次第に、狭い複数の閾値電圧範囲を割り当てるステップを含む、
ことを特徴とする請求項4に記載の方法。 - 各範囲内の予期された電荷損失もしくは電荷獲得に従って、前記複数の閾値範囲を調整するステップをさらに含む、
ことを特徴とする請求項1に記載の方法。 - 前記マルチレベルセルメモリはメモリデバイスの一部であり、ターゲットメモリセルの閾値電圧を増加させるために前記ターゲットメモリセルへ複数のプログラミングパルスを印加することによって、前記ターゲットメモリセルをプログラムするステップと、閾値電圧が所望の閾値電圧よりも低い場合には、前記ターゲットメモリセルへ複数のプログラミングパルスを再度印加するステップとをさらに含み、前記閾値電圧は、各々の閾値電圧に依存して、異なる大きさの複数の閾値電圧範囲のうちの一つ内にある、
ことを特徴とする請求項1に記載の方法。 - 印加するステップは、前記ターゲットメモリセルの前記閾値電圧を、最低の所望閾値電圧に対する最大の閾値電圧範囲から、最高の所望閾値電圧に対する最小の閾値電圧範囲の間の大きさの範囲へと設定するために、複数のパルスを印加するステップをさらに含む、
ことを特徴とする請求項7に記載の方法。 - セルごとに複数レベルを各々格納することが可能なメモリセルのアレイと、
前記メモリセルのアレイの制御および/もしくはアクセスのための回路と、
を含み、
前記制御回路は、複数の閾値電圧範囲のうちの一つの範囲内の閾値電圧へとメモリセルをプログラムするよう適応され、前記複数の閾値電圧範囲の各々は異なるデータ値に対応し、前記複数の閾値電圧範囲のうちの少なくとも二つは不均等な大きさである、
ことを特徴とするメモリデバイス。 - 前記複数の範囲は、最低の閾値電圧に対する最大の閾値電圧範囲から、最高の閾値電圧に対する最小の閾値電圧範囲の間の大きさに定められる、
ことを特徴とする請求項9に記載のデバイス。 - 前記メモリデバイスはソリッドステートメモリデバイスである、
ことを特徴とする請求項9に記載のデバイス。 - 前記ソリッドステートメモリデバイスは、NANDソリッドステートメモリデバイスである、
ことを特徴とする請求項11に記載のデバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US11/869,868 | 2007-10-10 | ||
US11/869,868 US7639532B2 (en) | 2007-10-10 | 2007-10-10 | Non-equal threshold voltage ranges in MLC NAND |
PCT/US2008/079124 WO2009048898A1 (en) | 2007-10-10 | 2008-10-08 | Non-equal threshold voltage ranges in mlc nand |
Publications (2)
Publication Number | Publication Date |
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JP2011501335A true JP2011501335A (ja) | 2011-01-06 |
JP5483204B2 JP5483204B2 (ja) | 2014-05-07 |
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JP2010528984A Active JP5483204B2 (ja) | 2007-10-10 | 2008-10-08 | Mlcnandにおける不均等閾値電圧範囲 |
Country Status (6)
Country | Link |
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US (1) | US7639532B2 (ja) |
EP (2) | EP2597648B1 (ja) |
JP (1) | JP5483204B2 (ja) |
KR (1) | KR101154624B1 (ja) |
CN (1) | CN101821811B (ja) |
WO (1) | WO2009048898A1 (ja) |
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EP2597648A3 (en) | 2015-05-06 |
US7639532B2 (en) | 2009-12-29 |
CN101821811A (zh) | 2010-09-01 |
EP2210256B1 (en) | 2013-01-23 |
JP5483204B2 (ja) | 2014-05-07 |
US20090097311A1 (en) | 2009-04-16 |
CN101821811B (zh) | 2015-02-04 |
EP2597648A2 (en) | 2013-05-29 |
EP2597648B1 (en) | 2018-03-28 |
KR101154624B1 (ko) | 2012-06-11 |
EP2210256A1 (en) | 2010-07-28 |
EP2210256A4 (en) | 2010-12-22 |
WO2009048898A1 (en) | 2009-04-16 |
KR20100077193A (ko) | 2010-07-07 |
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