JP2011199288A5 - - Google Patents

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Publication number
JP2011199288A5
JP2011199288A5 JP2011058010A JP2011058010A JP2011199288A5 JP 2011199288 A5 JP2011199288 A5 JP 2011199288A5 JP 2011058010 A JP2011058010 A JP 2011058010A JP 2011058010 A JP2011058010 A JP 2011058010A JP 2011199288 A5 JP2011199288 A5 JP 2011199288A5
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JP
Japan
Prior art keywords
die
interposer
laminate layer
layer
electrical signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011058010A
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English (en)
Japanese (ja)
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JP5327654B2 (ja
JP2011199288A (ja
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Publication date
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Publication of JP2011199288A publication Critical patent/JP2011199288A/ja
Publication of JP2011199288A5 publication Critical patent/JP2011199288A5/ja
Application granted granted Critical
Publication of JP5327654B2 publication Critical patent/JP5327654B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2011058010A 2010-03-18 2011-03-16 インタポーザを備える装置および方法 Expired - Fee Related JP5327654B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US31531910P 2010-03-18 2010-03-18
US61/315,319 2010-03-18

Publications (3)

Publication Number Publication Date
JP2011199288A JP2011199288A (ja) 2011-10-06
JP2011199288A5 true JP2011199288A5 (enExample) 2013-01-17
JP5327654B2 JP5327654B2 (ja) 2013-10-30

Family

ID=44602547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011058010A Expired - Fee Related JP5327654B2 (ja) 2010-03-18 2011-03-16 インタポーザを備える装置および方法

Country Status (4)

Country Link
US (1) US8338934B2 (enExample)
JP (1) JP5327654B2 (enExample)
CN (1) CN102194705B (enExample)
TW (1) TWI560824B (enExample)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5460388B2 (ja) * 2010-03-10 2014-04-02 新光電気工業株式会社 半導体装置及びその製造方法
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US8729714B1 (en) * 2012-12-31 2014-05-20 Intel Mobile Communications GmbH Flip-chip wafer level package and methods thereof
US9041207B2 (en) * 2013-06-28 2015-05-26 Intel Corporation Method to increase I/O density and reduce layer counts in BBUL packages
US9543373B2 (en) * 2013-10-23 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
KR101607981B1 (ko) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지
US9852998B2 (en) 2014-05-30 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Ring structures in device die
US9418965B1 (en) 2014-10-27 2016-08-16 Altera Corporation Embedded interposer with through-hole vias
US9633934B2 (en) * 2014-11-26 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semicondutor device and method of manufacture
US9515017B2 (en) * 2014-12-18 2016-12-06 Intel Corporation Ground via clustering for crosstalk mitigation
CN104485320A (zh) * 2014-12-30 2015-04-01 华天科技(西安)有限公司 一种有垂直通孔的埋入式传感芯片封装结构及其制备方法
CN105097726B (zh) * 2015-06-16 2019-03-12 合肥矽迈微电子科技有限公司 封装结构及封装方法
US9984998B2 (en) * 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
US9922895B2 (en) * 2016-05-05 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with tilted interface between device die and encapsulating material
CN105934095B (zh) * 2016-06-28 2019-02-05 Oppo广东移动通信有限公司 Pcb板及具有其的移动终端
JP2018018936A (ja) * 2016-07-27 2018-02-01 イビデン株式会社 配線基板
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
WO2018063383A1 (en) 2016-09-30 2018-04-05 Intel Corporation Active package substrate having anisotropic conductive layer
WO2018063384A1 (en) * 2016-09-30 2018-04-05 Intel Corporation Active package substrate having embedded interposer
JP6822192B2 (ja) * 2017-02-13 2021-01-27 Tdk株式会社 電子部品内蔵基板
US10687419B2 (en) * 2017-06-13 2020-06-16 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10872885B2 (en) * 2017-06-30 2020-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods of forming same
DE102018108409B4 (de) 2017-06-30 2023-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte schaltkreis-packages und verfahren zu deren herstellung
CN109786362B (zh) * 2017-11-14 2021-01-05 旺宏电子股份有限公司 无焊垫外扇晶粒叠层结构及其制作方法
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
EP3807927A4 (en) * 2018-06-13 2022-02-23 Invensas Bonding Technologies, Inc. TSV AS PAD
CN111415908B (zh) * 2019-01-07 2022-02-22 台达电子企业管理(上海)有限公司 电源模块、芯片嵌入式封装模块及制备方法
US11239193B2 (en) * 2020-01-17 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11450615B2 (en) * 2020-06-12 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
CN113838829B (zh) * 2020-06-23 2025-01-24 欣兴电子股份有限公司 封装载板及其制作方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5866952A (en) * 1995-11-30 1999-02-02 Lockheed Martin Corporation High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate
JP2000223645A (ja) * 1999-02-01 2000-08-11 Mitsubishi Electric Corp 半導体装置
US7161239B2 (en) * 2000-12-22 2007-01-09 Broadcom Corporation Ball grid array package enhanced with a thermal and electrical connector
US7202556B2 (en) * 2001-12-20 2007-04-10 Micron Technology, Inc. Semiconductor package having substrate with multi-layer metal bumps
SG104293A1 (en) * 2002-01-09 2004-06-21 Micron Technology Inc Elimination of rdl using tape base flip chip on flex for die stacking
US6506633B1 (en) * 2002-02-15 2003-01-14 Unimicron Technology Corp. Method of fabricating a multi-chip module package
TWI334638B (en) * 2005-12-30 2010-12-11 Ind Tech Res Inst Structure and process of chip package
SG135074A1 (en) * 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
US20080142946A1 (en) * 2006-12-13 2008-06-19 Advanced Chip Engineering Technology Inc. Wafer level package with good cte performance
TWI341577B (en) * 2007-03-27 2011-05-01 Unimicron Technology Corp Semiconductor chip embedding structure
US7687899B1 (en) * 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
JP5101240B2 (ja) * 2007-10-25 2012-12-19 日本特殊陶業株式会社 板状部品内蔵配線基板
US8230589B2 (en) * 2008-03-25 2012-07-31 Intel Corporation Method of mounting an optical device
JP2009289802A (ja) * 2008-05-27 2009-12-10 Tdk Corp 電子部品内蔵モジュール及びその製造方法
FR2938976A1 (fr) 2008-11-24 2010-05-28 St Microelectronics Grenoble Dispositif semi-conducteur a composants empiles
US8900921B2 (en) * 2008-12-11 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV

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