JP2011171529A - 電力用半導体素子 - Google Patents
電力用半導体素子 Download PDFInfo
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- JP2011171529A JP2011171529A JP2010034284A JP2010034284A JP2011171529A JP 2011171529 A JP2011171529 A JP 2011171529A JP 2010034284 A JP2010034284 A JP 2010034284A JP 2010034284 A JP2010034284 A JP 2010034284A JP 2011171529 A JP2011171529 A JP 2011171529A
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- semiconductor element
- connection terminal
- electrode
- power semiconductor
- core material
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Abstract
【解決手段】ワイドバンドギャップ半導体素子基板1に電極4、5が積層されると共に、電極5には外部配線へ接続するための接続端子6が接合されており、150℃以上の温度環境下で作動可能な電力用半導体素子であって、電極5、接続端子6を形成する芯材、及び前記半導体素子基板1の3つの線膨脹係数の差が、最大で5.2×10-6/Kであり、かつ、接続端子6と電極5とが直接接合されてなる接合部を有する電力用半導体素子。
【選択図】図1
Description
図1は本発明の第1の実施例を示す構成図である。図中の1は炭化珪素基板(線膨係数:4.2×10-6/K)であり、4H、n型、厚さ約200μmであってサイズが5mm×5mmの正方形材料である。図中の2は炭化珪素のホモエピタキシャル層であって、厚さは10μm程度とした。エピタキシャル層2の上にはスパッタにより厚さ1μmのモリブデン膜(線膨張係数:4.9×10-6/K)3を形成し、ショットキー電極とした。また、図中の4はスパッタで形成した厚さ0.3μmのニッケル膜であり、ニッケル膜4を形成後1000℃で2分間程度の熱処理を施して、炭化珪素基板(半導体素子基板)1裏面のオーミックを形成した。さらにニッケル膜4の表面にスパッタによりモリブデン金属(膜)5を厚さ2μm程度形成した。
2.エピタキシャル層
3.モリブデン膜
4.Ni膜
5.モリブデン膜
6.ブスバー
7.接続線
8.接合部位
9.GaN基板
10.エピタキシャル層
11.パラジウム膜
12.タングステン膜
13.チタン金多層膜
14.タングステン膜
15.ブスバー
16.ブスバー
Claims (7)
- ワイドバンドギャップ半導体素子基板に電極が積層されると共に、該電極には外部配線へ接続するための接続端子が接合されており、150℃以上の温度環境下で作動可能な電力用半導体素子であって、
前記電極、接続端子を形成する芯材、及び前記半導体素子基板の3つの線膨脹係数の差が、最大で5.2×10-6/Kであり、かつ、
前記接続端子と電極とが直接接合されてなる接合部を有することを特徴とする電力用半導体素子。 - 前記接続端子を形成する芯材が、モリブデン、タングステン、又は、それらの合金からなる請求項1記載の電力用半導体素子。
- 前記接続端子を形成する芯材が、モリブデン、タングステン、または、それらの合金からなり、かつ、該芯材の表面に、電気抵抗率が4×10-8Ω・m以下の金属が被膜されて接続端子が形成される請求項1又は2に記載の電力用半導体素子。
- 前記接続端子の横断面における前記金属被膜の面積が、該横断面に対して70%以下である請求項3に記載の電力用半導体素子。
- 前記半導体素子基板が、炭化珪素、窒化ガリウム、又は、ダイヤモンドからなる請求項1〜4のいずれかに記載の電力用半導体素子。
- 前記電極と接続端子との接合部が、超音波振動により接合してなる接合部である請求項1〜5のいずれかに記載の電力用半導体素子。
- 前記電極が、モリブデン、タングステン、又は、それらの合金からなる請求項1〜6のいずれかに記載の電力用半導体素子。
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JP2010034284A JP4795471B2 (ja) | 2010-02-19 | 2010-02-19 | 電力用半導体素子 |
PCT/JP2011/054215 WO2011102547A1 (ja) | 2010-02-19 | 2011-02-18 | 電力用半導体素子 |
US13/578,842 US8901569B2 (en) | 2010-02-19 | 2011-02-18 | Power semiconductor device |
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