JP2011044654A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2011044654A
JP2011044654A JP2009193318A JP2009193318A JP2011044654A JP 2011044654 A JP2011044654 A JP 2011044654A JP 2009193318 A JP2009193318 A JP 2009193318A JP 2009193318 A JP2009193318 A JP 2009193318A JP 2011044654 A JP2011044654 A JP 2011044654A
Authority
JP
Japan
Prior art keywords
interposer
pad
chips
pads
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009193318A
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English (en)
Japanese (ja)
Other versions
JP2011044654A5 (https=
Inventor
Akinori Shiraishi
晶紀 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009193318A priority Critical patent/JP2011044654A/ja
Publication of JP2011044654A publication Critical patent/JP2011044654A/ja
Publication of JP2011044654A5 publication Critical patent/JP2011044654A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/859—Bump connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
JP2009193318A 2009-08-24 2009-08-24 半導体装置 Pending JP2011044654A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009193318A JP2011044654A (ja) 2009-08-24 2009-08-24 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009193318A JP2011044654A (ja) 2009-08-24 2009-08-24 半導体装置

Publications (2)

Publication Number Publication Date
JP2011044654A true JP2011044654A (ja) 2011-03-03
JP2011044654A5 JP2011044654A5 (https=) 2012-08-09

Family

ID=43831837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009193318A Pending JP2011044654A (ja) 2009-08-24 2009-08-24 半導体装置

Country Status (1)

Country Link
JP (1) JP2011044654A (https=)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015220291A (ja) * 2014-05-15 2015-12-07 株式会社ソシオネクスト 半導体装置及びその製造方法
JP2016018876A (ja) * 2014-07-08 2016-02-01 日本電気株式会社 電子装置又はその製造方法
CN107041137A (zh) * 2014-09-05 2017-08-11 英帆萨斯公司 多芯片模块及其制法
US9875969B2 (en) 2009-06-24 2018-01-23 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US10283434B2 (en) 2015-11-04 2019-05-07 Fujitsu Limited Electronic device, method for manufacturing the electronic device, and electronic apparatus
JP2021093515A (ja) * 2019-12-06 2021-06-17 インテル・コーポレーション 再構成ウェハアセンブリ
CN113948508A (zh) * 2021-10-12 2022-01-18 天津津航计算技术研究所 一种基于硅载板的芯片模块高密度互连方法
DE102014116417B4 (de) 2013-12-18 2022-01-27 Intel Corporation Paket integrierter Schaltungen mit eingebetteter Brücke, Verfahren zum Zusammenbau eines solchen und Paketzusammensetzung
CN116053229A (zh) * 2022-03-17 2023-05-02 海光信息技术股份有限公司 芯片封装基板和封装芯片
WO2024053103A1 (ja) * 2022-09-09 2024-03-14 ウルトラメモリ株式会社 Ｉｃブリッジ、ｉｃモジュールおよびｉｃモジュールの製造方法
US12446159B2 (en) 2021-05-26 2025-10-14 Murata Manufacturing Co., Ltd. Electronic circuit module

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223651A (ja) * 1999-01-28 2000-08-11 United Microelectronics Corp 対向マルチチップ用パッケージ
JP2001244388A (ja) * 2000-02-28 2001-09-07 Matsushita Electric Ind Co Ltd 半導体装置
JP2003303847A (ja) * 2002-04-10 2003-10-24 Kaijo Corp 半導体構造およびボンディング方法
JP2006073651A (ja) * 2004-08-31 2006-03-16 Fujitsu Ltd 半導体装置
JP2006261311A (ja) * 2005-03-16 2006-09-28 Sony Corp 半導体装置及びその製造方法
JP2008270446A (ja) * 2007-04-19 2008-11-06 Toshiba Corp 積層型半導体装置とその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223651A (ja) * 1999-01-28 2000-08-11 United Microelectronics Corp 対向マルチチップ用パッケージ
JP2001244388A (ja) * 2000-02-28 2001-09-07 Matsushita Electric Ind Co Ltd 半導体装置
JP2003303847A (ja) * 2002-04-10 2003-10-24 Kaijo Corp 半導体構造およびボンディング方法
JP2006073651A (ja) * 2004-08-31 2006-03-16 Fujitsu Ltd 半導体装置
JP2006261311A (ja) * 2005-03-16 2006-09-28 Sony Corp 半導体装置及びその製造方法
JP2008270446A (ja) * 2007-04-19 2008-11-06 Toshiba Corp 積層型半導体装置とその製造方法

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10763216B2 (en) 2009-06-24 2020-09-01 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US9875969B2 (en) 2009-06-24 2018-01-23 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US10510669B2 (en) 2009-06-24 2019-12-17 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US11824008B2 (en) 2009-06-24 2023-11-21 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US10923429B2 (en) 2009-06-24 2021-02-16 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
DE112010002705B4 (de) 2009-06-24 2021-11-11 Intel Corporation Multi-Chip-Baugruppe und Verfahren zur Bereitstellung von Chip-Chip-Zwischenverbindungen in derselben
US12113026B2 (en) 2009-06-24 2024-10-08 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US11876053B2 (en) 2009-06-24 2024-01-16 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
DE102014116417B4 (de) 2013-12-18 2022-01-27 Intel Corporation Paket integrierter Schaltungen mit eingebetteter Brücke, Verfahren zum Zusammenbau eines solchen und Paketzusammensetzung
JP2015220291A (ja) * 2014-05-15 2015-12-07 株式会社ソシオネクスト 半導体装置及びその製造方法
JP2016018876A (ja) * 2014-07-08 2016-02-01 日本電気株式会社 電子装置又はその製造方法
CN107041137A (zh) * 2014-09-05 2017-08-11 英帆萨斯公司 多芯片模块及其制法
US10283434B2 (en) 2015-11-04 2019-05-07 Fujitsu Limited Electronic device, method for manufacturing the electronic device, and electronic apparatus
JP2021093515A (ja) * 2019-12-06 2021-06-17 インテル・コーポレーション 再構成ウェハアセンブリ
US12446159B2 (en) 2021-05-26 2025-10-14 Murata Manufacturing Co., Ltd. Electronic circuit module
CN113948508A (zh) * 2021-10-12 2022-01-18 天津津航计算技术研究所 一种基于硅载板的芯片模块高密度互连方法
CN116053229A (zh) * 2022-03-17 2023-05-02 海光信息技术股份有限公司 芯片封装基板和封装芯片
WO2024053103A1 (ja) * 2022-09-09 2024-03-14 ウルトラメモリ株式会社 Ｉｃブリッジ、ｉｃモジュールおよびｉｃモジュールの製造方法

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