JP2003303847A - 半導体構造およびボンディング方法 - Google Patents
半導体構造およびボンディング方法Info
- Publication number
- JP2003303847A JP2003303847A JP2002108144A JP2002108144A JP2003303847A JP 2003303847 A JP2003303847 A JP 2003303847A JP 2002108144 A JP2002108144 A JP 2002108144A JP 2002108144 A JP2002108144 A JP 2002108144A JP 2003303847 A JP2003303847 A JP 2003303847A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- semiconductor chip
- wire
- electrode pad
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- H01—ELECTRIC ELEMENTS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
のワイヤ高さを低くでき、パッケージの薄型化、小型化
を可能にした半導体装置のワイヤボンディング構造とワ
イヤボンディング方法を提供する。 【解決手段】 基板1上に実装された半導体チップ2の
電極パッド3と基板1上に形成された電極パッド4の間
を金属ワイヤ5で接続した半導体装置のワイヤボンディ
ング構造において、基板1上に実装された半導体チップ
2の電極パッド3上に金属バンプ7を形成し、これを所
定回繰り返すことにより半導体チップ2の電極パッド3
上に1つまたは複数個の金属バンプ7を積み重ねた状態
で形成した後、基板1上の電極パッド4を1次ボンディ
ング点、積み重ねられた金属バンプ7の最上段の金属バ
ンプ上面を2次ボンディング点として金属ワイヤ5をリ
バース法でボンディングした。
Description
化、小型化が可能な半導体構造とボンディング方法に関
する。
おいて、1はプリント基板,フィルム基板,リードフレ
ームなどの半導体チップ実装用の基板、2は基板1上に
実装された半導体チップ、3は半導体チップ2の上面周
縁に形成された電極パッド、4は基板1上に形成された
配線用の電極パッド、5は電極パッド3,4間にボンデ
ィングされた金線などの金属ワイヤである。
に半導体チップ2上の電極パッド3に金属ワイヤ5を1
次ボンディングした後、基板1上の電極パッド4に2次
ボンディングする、いわゆるフォワード法と呼ばれるワ
イヤボンディング方法によって配線したものである。
を挿通したキャピラリー(図示せず)を半導体チップ2
の電極パッド3の直上に位置させ、放電電極からの放電
によりキャピラリー先端から突出した金属ワイヤ5の先
端にボールを形成した後、キャピラリーを下降させて電
極パッド3に押圧することにより溶融したボールを電極
パッド3に1次ボンディングし、次いで、キャピラリー
を所定の軌跡に沿って基板1上の電極パッド4の直上ま
で移動させた後、該位置で電極パッド4に向けて下降さ
せ、押圧すると同時に超音波などを印加することにより
金属ワイヤ5をキャピラリー先端位置で電極パッド4に
2次ボンディングするものである。
においては、金属ワイヤ5に十分な接続強度を与えるた
め、金属ワイヤ5は1次ボンディング位置で一度所定距
離だけ垂直方向に立ち上がらせた後、2次ボンディング
位置に向けて折り曲げ配線する必要がある。このため、
半導体チップ2上の電極パッド3が1次ボンディング点
となるフォワード法の場合、チップ表面からのワイヤ高
さhがその分だけ高くなってしまい、それ以上薄型化す
ることができず、完成後の半導体パッケージの厚さが厚
くなってしまうという欠点があった。
すための1つの方法として、図7に示すように、まず最
初に基板1上の電極パッド4に金属ワイヤ5を1次ボン
ディングした後、半導体チップ2の電極パッド3に2次
ボンディングする、いわゆるリバース法と呼ばれるワイ
ヤボンディング方法が利用されている。
の高密度化、多電極化に伴い、電極パッドは、半導体チ
ップの上面周縁に沿って1列に並ぶだけでなく、その内
側にも二重あるいは三重に並んだ多重配列電極が採用さ
れるようになった。このような多重配列電極を備えた半
導体チップの場合、前記フォワード法やリバース法を利
用してワイヤボンディングしても、たとえば図8、図9
に示すように、外側の電極パッド3aにボンディングさ
れた金属ワイヤ5aについてはそれほど問題ないが、内
側の電極パッド3bに接続された金属ワイヤ5bについ
ては、外側の電極パッド3aにボンディングされた金属
ワイヤ5aとの接触を避けるため、ワイヤ間距離を十分
にとる必要があり、ワイヤ間距離を大きく取れるフォワ
ード法によってボンディングせざるを得なかった。この
ため、チップ面からのワイヤ高さhをある程度以下に低
くすることが難しかった。
れたもので、多重配列電極の場合であってもチップ面か
らのワイヤ高さを低くでき、パッケージの薄型化、小型
化を可能にした半導体構造とボンディング方法を提供す
ることを目的とするものである。
め、本発明は次のような手段を採用した。すなわち、請
求項1に係る半導体構造は、基板上に実装された半導体
チップの電極パッド上に金属バンプが1つまたは複数個
積み重ねた状態で形成されており、該積み重ねられた金
属バンプの最上段の金属バンプ上面と基板上の電極パッ
ドの間、または該積み重ねられた金属バンプの最上段の
金属バンプ上面と他の半導体チップの電極パッドの間を
金属ワイヤでボンディングしたことを特徴とするもので
ある。
は、基板上に実装された半導体チップの電極パッド上に
金属バンプを形成し、これを所定回繰り返すことによっ
て半導体チップの電極パッド上に1つまたは複数個の金
属バンプを積み重ねた状態で形成した後、該積み重ねら
れた金属バンプの最上段の金属バンプ上面を2次ボンデ
ィング点、基板上の電極パッドまたは他の半導体チップ
の電極パッドを1次ボンディング点として、これらの間
を金属ワイヤでボンディングすることを特徴とするもの
である。
ング方法を採用した場合、金属バンプの積み重ね段数に
よってチップ面からのワイヤ高さを自在に調整すること
ができる。このため、多重配列電極の場合であってもチ
ップ面からのワイヤ高さを金属バンプの数によって調整
することができ、半導体パッケージの薄型化、小型化を
図ることができる。
て図面を参照して説明する。図1に本発明に係る半導体
構造の第1の実施の形態を示す。なお、前述した従来例
と同一の部分には同一の符号を付して示した。
導体構造の基本形態を示すもので、半導体チップ2の電
極パッド3の上に3個の金属バンプ7を3段に積み重ね
て形成し、この3段に積み重ねられた3個の金属バンプ
7の最上段の金属バンプの上面を2次ボンディング点、
基板1上の電極パッド4を1次ボンディング点として金
属ワイヤ5をボンディングしたものである。
ンプ7の段数を変えることにより、チップ表面からのワ
イヤ高さhを自在に変えることが可能となり、後述する
第2および第3の実施の形態からさらに明らかとなるよ
うに、半導体チップ2の電極パッド3が半導体チップ2
の上面周縁に沿って1列に並ぶだけでなく、その内側に
も二重あるいは三重に並んだ多重配列電極の場合でも、
チップ表面からのワイヤ高さhを最小に押さえることが
可能となる。なお、金属バンプ7の積み重ね段数は3段
に限られものではなく、製造する半導体装置の仕様に応
じて決定されるものである。
のボンディング方法を図2によって説明する。なお、本
発明のボンディング方法は、以下に示すように、従来か
ら用いられている既設のワイヤボンディング装置を用い
て実現することができる。
どの金属ワイヤ5を挿通したキャピラリー8を半導体チ
ップ2の電極パッド3の直上に位置させ、放電電極9か
らの放電により、キャピラリー先端から突出した金属ワ
イヤ5の先端にボール6を形成する。
ー8を下降させ、溶融したボール6を電極パッド3に押
圧して融着させた後、(c)に示すように、図示しない
クランプによって金属ワイヤ5をつかんだ状態でキャピ
ラリー8を上方へ引き上げ、金属ワイヤ5を引きちぎる
ことによって金属パッド3上に金属バンプ7を形成す
る。上記操作を必要回数、例えば図2の例の場合には3
回繰り返すことにより、(d)に示すように、金属パッ
ド3上に3段重ねされた3個の金属バンプ7が形成され
る。
ンディング点、前記3段に積み重ねられた3個の金属バ
ンプ7の最上段の金属バンプの上面を2次ボンディング
点として、前述したリバース法によって金属ワイヤ5を
ボンディングする。
ワイヤ5を挿通したキャピラリー8を基板1の電極パッ
ド4の直上に位置させ、放電電極9からの放電により、
キャピラリー先端から突出した金属ワイヤ5の先端にボ
ール6を形成する。
ー8を下降させ、溶融したボール6を電極パッド4に押
圧して融着させた後、キャピラリー8を所定距離だけ垂
直方向に立ち上がらせ、(g)に示すように、所定の軌
跡に沿って2次ボンディング点である半導体チップ2の
電極パッド3の方向に向けて移動させる。そして、電極
パッド3の直上に達したら、再びキャピラリー8を下降
させ、金属ワイヤ5を3個の金属バンプ7の最上段の金
属バンプ上面に所定の圧力で押しつけながら超音波など
を加えることにより、金属ワイヤ5をキャピラリー先端
位置で最上段の金属バンプ7の上面に2次ボンディング
する。
クランプによって金属ワイヤ5をつかんだ状態でキャピ
ラリー8を上方へ引き上げることにより、金属ワイヤ5
を引きちぎり、2次ボンディングを終了する。このよう
にして、図1に示したワイヤボンディング構造が完成す
る。
の実施の形態を示す。この第2の実施の形態は、半導体
チップ2の金属パッド3a,3bが内外2列配置されて
いる半導体装置の場合の例を示すものである。
側に位置する第1の電極パッド3aと基板1上の対応す
る電極パッド4aについては、従来と同様に、基板1の
電極パッド4aを1次ボンディング点、半導体チップ2
の電極パッド3aを2次ボンディング点とするリバース
法によってワイヤボンディングされている。
位置する第2の電極パッド3bと基板1上の対応する電
極パッド4bについては、半導体チップ2の電極パッド
3b上に金属バンプ7を2段に重ねて形成した後、基板
1上の電極パッド4bを1次ボンディング点、前記2段
に積み重ねられた金属バンプ7の最上段の金属バンプ上
面を2次ボンディング点として金属ワイヤ5bをリバー
ス法によってワイヤボンディングしたものである。
体チップ2の電極パッド3a,3bが内外2列に配置と
されているにもかかわらず、チップ面からのワイヤ高さ
hを低くすることができ、従来の半導体装置に比べてパ
ッケージの薄型化、小型化を図ることができる。
実施の形態を示す。この第3の実施の形態は、前記第2
の実施の形態と同様な構造において、半導体チップ2と
基板1上の電極パッド4aとの間に高さの高い電子部品
10が実装されている場合の例を示すものである。
極パッド4aとの間に高さの高い電子部品10が実装さ
れているような場合には、通常のリバース法では金属ワ
イヤ5aが電子部品10に接触するおそれがあるが、本
発明の場合には、図示するように、半導体チップ2の上
面周縁の外側に位置する第1の電極パッド3a上に金属
バンプ7を所定段数(図示例では1段)形成した後、基
板1上の電極パッド4aを1次ボンディング点、前記電
極パッド3a上に形成された金属バンプ7の上面を2次
ボンディング点として金属ワイヤ5aをボンディングす
ればよい。
れば、半導体チップと基板上の電極パッドとの間に他の
電子部品が実装されているような場合でも、この電子部
品を避けながら、チップ面からのワイヤ高さhを可能な
限り低く設定することができる。
実施の形態を示す。この第4の実施の形態は本発明の応
用例を示すもので、本発明の方法によってワイヤボンデ
ィングされた半導体チップ2上に、さらに金属バンプを
利用して他の半導体チップをフリップチップ実装した場
合の例を示すものである。
されている半導体チップ2の電極パッド3上に金属バン
プ7を形成し、基板1上の電極パッド4を1次ボンディ
ング点、前記金属バンプ7を2次ボンディング点として
金属ワイヤ5をボンディングした後、さらに、この2次
ボンディング点の上に金属バンプ7を2段に積み重ねて
形成し、この3段重ねした金属バンプ7の上に、フリッ
プチップ型の半導体チップ11をその電極パッド12が
接触した状態で載せ、熱などを加えることによって半導
体チップ2上に半導体チップ11をフリップチップ実装
したものである。このようなワイヤボンディング構造と
した場合、ワイヤボンディング構造とフリップチップ構
造を備えた複合タイプの半導体装置を簡単に製造するこ
とができる。
ップの電極パッドと基板上の電極パッド間を接続する場
合を例に採って説明したが、ボンディング点はこれらの
間に限定されるものではなく、基板上に実装された半導
体チップ同士の電極パッド間を接続することもできる。
この場合、前記金属バンプを積み重ねられた半導体チッ
プの電極パッドが2次ボンディング点、他の半導体チッ
プの電極パッドが1次ボンディング点となる。
半導体チップの電極パッド上に金属バンプを形成し、こ
の金属バンプの上に金属ワイヤをボンディングするよう
にしたので、チップ面からのワイヤ高さを自在に調整す
ることができる。このため、半導体チップの電極バッド
が多重配列されているような場合であっても、チップ面
からのワイヤ高さを可能な限り低くでき、半導体パッケ
ージの薄型化、小型化を図ることができる。また、既設
のワイヤボンディング装置を利用してボンディングを行
うことができるので、設備投資が少なくて済み、コスト
増を抑えながら半導体パッケージの薄型化、小型化を図
ることができる。
示す略示側面図である。
法の説明図である。
示す略示側面図である。
示す略示側面図である。
示す略示側面図である。
である。
である。
である。
である。
Claims (2)
- 【請求項1】 基板上に実装された半導体チップの電極
パッド上に金属バンプが1つまたは複数個積み重ねた状
態で形成されており、該積み重ねられた金属バンプの最
上段の金属バンプ上面と基板上の電極パッドの間、また
は該積み重ねられた金属バンプの最上段の金属バンプ上
面と他の半導体チップの電極パッドの間を金属ワイヤで
ボンディングしたことを特徴とする半導体構造。 - 【請求項2】 基板上に実装された半導体チップの電極
パッド上に金属バンプを形成し、これを所定回繰り返す
ことによって半導体チップの電極パッド上に1つまたは
複数個の金属バンプを積み重ねた状態で形成した後、該
積み重ねられた金属バンプの最上段の金属バンプ上面を
2次ボンディング点、基板上の電極パッドまたは他の半
導体チップの電極パッドを1次ボンディング点として、
これらの間を金属ワイヤでボンディングすることを特徴
とするボンディング方法。
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US7521810B2 (en) | 2005-08-11 | 2009-04-21 | Samsung Electronics Co., Ltd. | Chip stack package and manufacturing method thereof |
JP2007234960A (ja) * | 2006-03-02 | 2007-09-13 | Epson Toyocom Corp | 電子デバイスおよびその製造方法 |
JP2007250906A (ja) * | 2006-03-16 | 2007-09-27 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2008034567A (ja) * | 2006-07-27 | 2008-02-14 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2008098549A (ja) * | 2006-10-16 | 2008-04-24 | Kaijo Corp | 半導体装置 |
WO2008047665A1 (fr) * | 2006-10-16 | 2008-04-24 | Kaijo Corporation | Dispositif semi-conducteur |
JP2010141112A (ja) * | 2008-12-11 | 2010-06-24 | Sharp Corp | 半導体装置および半導体装置の製造方法 |
JP2011044654A (ja) * | 2009-08-24 | 2011-03-03 | Shinko Electric Ind Co Ltd | 半導体装置 |
US20220001475A1 (en) * | 2018-11-06 | 2022-01-06 | Mbda France | Method for connection by brazing enabling improved fatigue resistance of brazed joints |
US12070812B2 (en) * | 2018-11-06 | 2024-08-27 | Mbda France | Method for connection by brazing enabling improved fatigue resistance of brazed joints |
JP2022047892A (ja) * | 2020-09-14 | 2022-03-25 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP7412310B2 (ja) | 2020-09-14 | 2024-01-12 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
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