JP2011029345A5 - - Google Patents
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- Publication number
- JP2011029345A5 JP2011029345A5 JP2009172516A JP2009172516A JP2011029345A5 JP 2011029345 A5 JP2011029345 A5 JP 2011029345A5 JP 2009172516 A JP2009172516 A JP 2009172516A JP 2009172516 A JP2009172516 A JP 2009172516A JP 2011029345 A5 JP2011029345 A5 JP 2011029345A5
- Authority
- JP
- Japan
- Prior art keywords
- region
- formation region
- transistor
- channel formation
- opposing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015572 biosynthetic process Effects 0.000 claims 7
- 238000002955 isolation Methods 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 230000002093 peripheral effect Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009172516A JP5537078B2 (ja) | 2009-07-23 | 2009-07-23 | 半導体装置 |
| US12/826,037 US8432003B2 (en) | 2009-07-23 | 2010-06-29 | Semiconductor device |
| US13/849,998 US8847330B2 (en) | 2009-07-23 | 2013-03-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009172516A JP5537078B2 (ja) | 2009-07-23 | 2009-07-23 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011029345A JP2011029345A (ja) | 2011-02-10 |
| JP2011029345A5 true JP2011029345A5 (enExample) | 2012-04-05 |
| JP5537078B2 JP5537078B2 (ja) | 2014-07-02 |
Family
ID=43496530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009172516A Expired - Fee Related JP5537078B2 (ja) | 2009-07-23 | 2009-07-23 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US8432003B2 (enExample) |
| JP (1) | JP5537078B2 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5537078B2 (ja) * | 2009-07-23 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| KR102813105B1 (ko) * | 2021-03-17 | 2025-05-26 | 창신 메모리 테크놀로지즈 아이엔씨 | 집적회로 및 이의 배치 방법 |
| KR20220138914A (ko) * | 2021-04-06 | 2022-10-14 | 삼성전자주식회사 | 반도체 장치 및 메모리 장치 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4794030B2 (ja) | 2000-07-10 | 2011-10-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP3997089B2 (ja) * | 2002-01-10 | 2007-10-24 | 株式会社ルネサステクノロジ | 半導体装置 |
| JP2004241529A (ja) * | 2003-02-05 | 2004-08-26 | Matsushita Electric Ind Co Ltd | 半導体回路装置及びその回路シミュレーション方法 |
| JP4778689B2 (ja) * | 2004-06-16 | 2011-09-21 | パナソニック株式会社 | 標準セル、標準セルライブラリおよび半導体集積回路 |
| JP4309360B2 (ja) * | 2005-03-10 | 2009-08-05 | エルピーダメモリ株式会社 | 回路セル及び半導体装置 |
| JP2007027272A (ja) | 2005-07-13 | 2007-02-01 | Toshiba Corp | 半導体集積回路 |
| JP5091462B2 (ja) * | 2006-01-19 | 2012-12-05 | パナソニック株式会社 | セルおよび半導体装置 |
| US7446352B2 (en) * | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
| US7932545B2 (en) * | 2006-03-09 | 2011-04-26 | Tela Innovations, Inc. | Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers |
| US7943967B2 (en) * | 2006-03-09 | 2011-05-17 | Tela Innovations, Inc. | Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments |
| JP2007311491A (ja) * | 2006-05-17 | 2007-11-29 | Toshiba Corp | 半導体集積回路 |
| JP2007311587A (ja) * | 2006-05-19 | 2007-11-29 | Matsushita Electric Ind Co Ltd | 半導体装置 |
| JP2008218881A (ja) * | 2007-03-07 | 2008-09-18 | Nec Electronics Corp | 半導体装置 |
| US8053346B2 (en) * | 2007-04-30 | 2011-11-08 | Hynix Semiconductor Inc. | Semiconductor device and method of forming gate and metal line thereof with dummy pattern and auxiliary pattern |
| JP2008311361A (ja) * | 2007-06-13 | 2008-12-25 | Nec Electronics Corp | 半導体集積回路、半導体集積回路のレイアウト設計方法、及び半導体集積回路の自動レイアウトプログラム |
| JP5638760B2 (ja) * | 2008-08-19 | 2014-12-10 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP5537078B2 (ja) * | 2009-07-23 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2009
- 2009-07-23 JP JP2009172516A patent/JP5537078B2/ja not_active Expired - Fee Related
-
2010
- 2010-06-29 US US12/826,037 patent/US8432003B2/en not_active Expired - Fee Related
-
2013
- 2013-03-25 US US13/849,998 patent/US8847330B2/en active Active
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