JP5537078B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP5537078B2
JP5537078B2 JP2009172516A JP2009172516A JP5537078B2 JP 5537078 B2 JP5537078 B2 JP 5537078B2 JP 2009172516 A JP2009172516 A JP 2009172516A JP 2009172516 A JP2009172516 A JP 2009172516A JP 5537078 B2 JP5537078 B2 JP 5537078B2
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JP
Japan
Prior art keywords
region
transistor
dummy
formation region
semiconductor device
Prior art date
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Expired - Fee Related
Application number
JP2009172516A
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English (en)
Japanese (ja)
Other versions
JP2011029345A5 (enExample
JP2011029345A (ja
Inventor
俊英 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009172516A priority Critical patent/JP5537078B2/ja
Priority to US12/826,037 priority patent/US8432003B2/en
Publication of JP2011029345A publication Critical patent/JP2011029345A/ja
Publication of JP2011029345A5 publication Critical patent/JP2011029345A5/ja
Priority to US13/849,998 priority patent/US8847330B2/en
Application granted granted Critical
Publication of JP5537078B2 publication Critical patent/JP5537078B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2009172516A 2009-07-23 2009-07-23 半導体装置 Expired - Fee Related JP5537078B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009172516A JP5537078B2 (ja) 2009-07-23 2009-07-23 半導体装置
US12/826,037 US8432003B2 (en) 2009-07-23 2010-06-29 Semiconductor device
US13/849,998 US8847330B2 (en) 2009-07-23 2013-03-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009172516A JP5537078B2 (ja) 2009-07-23 2009-07-23 半導体装置

Publications (3)

Publication Number Publication Date
JP2011029345A JP2011029345A (ja) 2011-02-10
JP2011029345A5 JP2011029345A5 (enExample) 2012-04-05
JP5537078B2 true JP5537078B2 (ja) 2014-07-02

Family

ID=43496530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009172516A Expired - Fee Related JP5537078B2 (ja) 2009-07-23 2009-07-23 半導体装置

Country Status (2)

Country Link
US (2) US8432003B2 (enExample)
JP (1) JP5537078B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5537078B2 (ja) * 2009-07-23 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置
KR102813105B1 (ko) * 2021-03-17 2025-05-26 창신 메모리 테크놀로지즈 아이엔씨 집적회로 및 이의 배치 방법
KR20220138914A (ko) * 2021-04-06 2022-10-14 삼성전자주식회사 반도체 장치 및 메모리 장치

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4794030B2 (ja) 2000-07-10 2011-10-12 ルネサスエレクトロニクス株式会社 半導体装置
JP3997089B2 (ja) * 2002-01-10 2007-10-24 株式会社ルネサステクノロジ 半導体装置
JP2004241529A (ja) * 2003-02-05 2004-08-26 Matsushita Electric Ind Co Ltd 半導体回路装置及びその回路シミュレーション方法
JP4778689B2 (ja) * 2004-06-16 2011-09-21 パナソニック株式会社 標準セル、標準セルライブラリおよび半導体集積回路
JP4309360B2 (ja) * 2005-03-10 2009-08-05 エルピーダメモリ株式会社 回路セル及び半導体装置
JP2007027272A (ja) 2005-07-13 2007-02-01 Toshiba Corp 半導体集積回路
JP5091462B2 (ja) * 2006-01-19 2012-12-05 パナソニック株式会社 セルおよび半導体装置
US7446352B2 (en) * 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7932545B2 (en) * 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US7943967B2 (en) * 2006-03-09 2011-05-17 Tela Innovations, Inc. Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
JP2007311491A (ja) * 2006-05-17 2007-11-29 Toshiba Corp 半導体集積回路
JP2007311587A (ja) * 2006-05-19 2007-11-29 Matsushita Electric Ind Co Ltd 半導体装置
JP2008218881A (ja) * 2007-03-07 2008-09-18 Nec Electronics Corp 半導体装置
US8053346B2 (en) * 2007-04-30 2011-11-08 Hynix Semiconductor Inc. Semiconductor device and method of forming gate and metal line thereof with dummy pattern and auxiliary pattern
JP2008311361A (ja) * 2007-06-13 2008-12-25 Nec Electronics Corp 半導体集積回路、半導体集積回路のレイアウト設計方法、及び半導体集積回路の自動レイアウトプログラム
JP5638760B2 (ja) * 2008-08-19 2014-12-10 ルネサスエレクトロニクス株式会社 半導体装置
JP5537078B2 (ja) * 2009-07-23 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
US20110018090A1 (en) 2011-01-27
US20130207164A1 (en) 2013-08-15
US8847330B2 (en) 2014-09-30
JP2011029345A (ja) 2011-02-10
US8432003B2 (en) 2013-04-30

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