JP2011009514A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2011009514A
JP2011009514A JP2009152259A JP2009152259A JP2011009514A JP 2011009514 A JP2011009514 A JP 2011009514A JP 2009152259 A JP2009152259 A JP 2009152259A JP 2009152259 A JP2009152259 A JP 2009152259A JP 2011009514 A JP2011009514 A JP 2011009514A
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JP
Japan
Prior art keywords
substrate
semiconductor device
main surface
manufacturing
conductive member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009152259A
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English (en)
Japanese (ja)
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JP2011009514A5 (https=
Inventor
Michiaki Sugiyama
道昭 杉山
Takashi Miwa
孝志 三輪
Tomokazu Ishikawa
智和 石川
Tatsuya Hirai
達也 平井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009152259A priority Critical patent/JP2011009514A/ja
Priority to US12/793,923 priority patent/US8138022B2/en
Publication of JP2011009514A publication Critical patent/JP2011009514A/ja
Publication of JP2011009514A5 publication Critical patent/JP2011009514A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/656—Fan-in layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2009152259A 2009-06-26 2009-06-26 半導体装置の製造方法 Pending JP2011009514A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009152259A JP2011009514A (ja) 2009-06-26 2009-06-26 半導体装置の製造方法
US12/793,923 US8138022B2 (en) 2009-06-26 2010-06-04 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009152259A JP2011009514A (ja) 2009-06-26 2009-06-26 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2011009514A true JP2011009514A (ja) 2011-01-13
JP2011009514A5 JP2011009514A5 (https=) 2012-04-05

Family

ID=43381193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009152259A Pending JP2011009514A (ja) 2009-06-26 2009-06-26 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US8138022B2 (https=)
JP (1) JP2011009514A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015018932A (ja) * 2013-07-11 2015-01-29 日本特殊陶業株式会社 配線基板
WO2021038986A1 (ja) * 2019-08-29 2021-03-04 昭和電工マテリアルズ株式会社 電子部品装置を製造する方法、及び電子部品装置

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101194092B1 (ko) * 2008-02-14 2012-10-24 미츠비시 쥬고교 가부시키가이샤 반도체 소자 모듈 및 그 제조 방법
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US9412689B2 (en) 2012-01-24 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packaging structure and method
JPWO2014184988A1 (ja) * 2013-05-16 2017-02-23 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
US9147662B1 (en) * 2013-12-20 2015-09-29 Stats Chippac Ltd. Integrated circuit packaging system with fiber-less substrate and method of manufacture thereof
KR101538573B1 (ko) * 2014-02-05 2015-07-21 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
TWI584430B (zh) * 2014-09-10 2017-05-21 矽品精密工業股份有限公司 半導體封裝件及其製法
JP5873152B1 (ja) * 2014-09-29 2016-03-01 日本特殊陶業株式会社 配線基板
JP6429647B2 (ja) * 2015-01-26 2018-11-28 ルネサスエレクトロニクス株式会社 半導体装置
CN108271408B (zh) 2015-04-01 2020-12-04 瓦亚视觉有限公司 使用被动和主动测量生成场景的三维地图
US11502030B2 (en) * 2016-09-02 2022-11-15 Octavo Systems Llc System and method of assembling a system
US10622340B2 (en) * 2016-11-21 2020-04-14 Samsung Electronics Co., Ltd. Semiconductor package
US10445928B2 (en) 2017-02-11 2019-10-15 Vayavision Ltd. Method and system for generating multidimensional maps of a scene using a plurality of sensors of various types
US11729915B1 (en) 2022-03-22 2023-08-15 Tactotek Oy Method for manufacturing a number of electrical nodes, electrical node module, electrical node, and multilayer structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002083897A (ja) * 2000-09-05 2002-03-22 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2002359323A (ja) * 2001-03-26 2002-12-13 Nec Corp 半導体装置及び半導体装置の製造方法
JP2006253587A (ja) * 2005-03-14 2006-09-21 Toshiba Corp 半導体装置及びその組立方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4204989B2 (ja) * 2004-01-30 2009-01-07 新光電気工業株式会社 半導体装置及びその製造方法
JP4520355B2 (ja) * 2005-04-19 2010-08-04 パナソニック株式会社 半導体モジュール
JP4551321B2 (ja) * 2005-07-21 2010-09-29 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP2007123454A (ja) * 2005-10-27 2007-05-17 Renesas Technology Corp 半導体装置及びその製造方法
US7504283B2 (en) * 2006-12-18 2009-03-17 Texas Instruments Incorporated Stacked-flip-assembled semiconductor chips embedded in thin hybrid substrate
JP5036397B2 (ja) * 2007-05-21 2012-09-26 新光電気工業株式会社 チップ内蔵基板の製造方法
JP2008300498A (ja) 2007-05-30 2008-12-11 Panasonic Corp 電子部品内蔵基板とこれを用いた電子機器、およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002083897A (ja) * 2000-09-05 2002-03-22 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2002359323A (ja) * 2001-03-26 2002-12-13 Nec Corp 半導体装置及び半導体装置の製造方法
JP2006253587A (ja) * 2005-03-14 2006-09-21 Toshiba Corp 半導体装置及びその組立方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015018932A (ja) * 2013-07-11 2015-01-29 日本特殊陶業株式会社 配線基板
WO2021038986A1 (ja) * 2019-08-29 2021-03-04 昭和電工マテリアルズ株式会社 電子部品装置を製造する方法、及び電子部品装置
JP6885527B1 (ja) * 2019-08-29 2021-06-16 昭和電工マテリアルズ株式会社 電子部品装置を製造する方法、及び電子部品装置

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US20100330742A1 (en) 2010-12-30
US8138022B2 (en) 2012-03-20

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