JP2010519723A5 - - Google Patents
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- Publication number
- JP2010519723A5 JP2010519723A5 JP2009537248A JP2009537248A JP2010519723A5 JP 2010519723 A5 JP2010519723 A5 JP 2010519723A5 JP 2009537248 A JP2009537248 A JP 2009537248A JP 2009537248 A JP2009537248 A JP 2009537248A JP 2010519723 A5 JP2010519723 A5 JP 2010519723A5
- Authority
- JP
- Japan
- Prior art keywords
- liner
- conductive
- interconnect
- diffusion barrier
- prevention
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002265 prevention Effects 0.000 claims 15
- 230000004888 barrier function Effects 0.000 claims 11
- 238000009792 diffusion process Methods 0.000 claims 11
- 239000003989 dielectric material Substances 0.000 claims 9
- 238000000034 method Methods 0.000 claims 8
- 229910052799 carbon Inorganic materials 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 2
- 238000005137 deposition process Methods 0.000 claims 2
- CNCZOAMEKQQFOA-HZQGBTCBSA-N 4-[(2s,3s,4r,5r,6r)-4,5-bis(3-carboxypropanoyloxy)-2-methyl-6-[[(2r,3r,4s,5r,6s)-3,4,5-tris(3-carboxypropanoyloxy)-6-[2-(3,4-dihydroxyphenyl)-5,7-dihydroxy-4-oxochromen-3-yl]oxyoxan-2-yl]methoxy]oxan-3-yl]oxy-4-oxobutanoic acid Chemical compound OC(=O)CCC(=O)O[C@@H]1[C@H](OC(=O)CCC(O)=O)[C@@H](OC(=O)CCC(O)=O)[C@H](C)O[C@H]1OC[C@@H]1[C@@H](OC(=O)CCC(O)=O)[C@H](OC(=O)CCC(O)=O)[C@@H](OC(=O)CCC(O)=O)[C@H](OC=2C(C3=C(O)C=C(O)C=C3OC=2C=2C=C(O)C(O)=CC=2)=O)O1 CNCZOAMEKQQFOA-HZQGBTCBSA-N 0.000 claims 1
- 235000003976 Ruta Nutrition 0.000 claims 1
- 240000005746 Ruta graveolens Species 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 150000002170 ethers Chemical class 0.000 claims 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 125000004430 oxygen atom Chemical group O* 0.000 claims 1
- 229920000412 polyarylene Polymers 0.000 claims 1
- 235000005806 ruta Nutrition 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- -1 silsesquioxane Inorganic materials 0.000 claims 1
- 229920001187 thermosetting polymer Polymers 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/560,044 US7569475B2 (en) | 2006-11-15 | 2006-11-15 | Interconnect structure having enhanced electromigration reliability and a method of fabricating same |
| US11/560,044 | 2006-11-15 | ||
| PCT/US2007/077975 WO2008060745A1 (en) | 2006-11-15 | 2007-09-10 | Interconnect structure having enhanced electromigration reliability and a method of fabricating same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010519723A JP2010519723A (ja) | 2010-06-03 |
| JP2010519723A5 true JP2010519723A5 (enExample) | 2010-07-15 |
| JP5274475B2 JP5274475B2 (ja) | 2013-08-28 |
Family
ID=39368439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009537248A Expired - Fee Related JP5274475B2 (ja) | 2006-11-15 | 2007-09-10 | エレクトロマイグレーションに対する向上した信頼度を有する相互接続構造体及びその製造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US7569475B2 (enExample) |
| EP (1) | EP2095409A4 (enExample) |
| JP (1) | JP5274475B2 (enExample) |
| KR (1) | KR101154748B1 (enExample) |
| CN (1) | CN101536170A (enExample) |
| WO (1) | WO2008060745A1 (enExample) |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100200991A1 (en) * | 2007-03-15 | 2010-08-12 | Rohan Akolkar | Dopant Enhanced Interconnect |
| US7777344B2 (en) * | 2007-04-11 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transitional interface between metal and dielectric in interconnect structures |
| US7956466B2 (en) * | 2008-05-09 | 2011-06-07 | International Business Machines Corporation | Structure for interconnect structure containing various capping materials for electrical fuse and other related applications |
| US8772156B2 (en) * | 2008-05-09 | 2014-07-08 | International Business Machines Corporation | Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications |
| US9024431B2 (en) | 2009-10-29 | 2015-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die contact structure and method |
| US8487447B2 (en) | 2011-05-19 | 2013-07-16 | International Business Machines Corporation | Semiconductor structure having offset passivation to reduce electromigration |
| US9029260B2 (en) * | 2011-06-16 | 2015-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gap filling method for dual damascene process |
| FR2979751A1 (fr) * | 2011-09-02 | 2013-03-08 | St Microelectronics Crolles 2 | Element metallique d'interconnexion dans une puce de circuit integre et procede de realisation |
| US8796853B2 (en) | 2012-02-24 | 2014-08-05 | International Business Machines Corporation | Metallic capped interconnect structure with high electromigration resistance and low resistivity |
| US9190348B2 (en) | 2012-05-30 | 2015-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scheme for connector site spacing and resulting structures |
| KR101985937B1 (ko) | 2012-07-11 | 2019-06-05 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
| US8835305B2 (en) | 2012-07-31 | 2014-09-16 | International Business Machines Corporation | Method of fabricating a profile control in interconnect structures |
| US9659869B2 (en) * | 2012-09-28 | 2017-05-23 | Intel Corporation | Forming barrier walls, capping, or alloys /compounds within metal lines |
| KR102057067B1 (ko) | 2013-01-29 | 2019-12-18 | 삼성전자주식회사 | 반도체 장치의 배선 구조체 및 그 형성 방법 |
| JP2015060918A (ja) * | 2013-09-18 | 2015-03-30 | 株式会社東芝 | 半導体装置 |
| US9362239B2 (en) * | 2014-10-21 | 2016-06-07 | Globalfoundries Inc. | Vertical breakdown protection layer |
| US9431343B1 (en) * | 2015-03-11 | 2016-08-30 | Samsung Electronics Co., Ltd. | Stacked damascene structures for microelectronic devices |
| US9418934B1 (en) | 2015-06-30 | 2016-08-16 | International Business Machines Corporation | Structure and fabrication method for electromigration immortal nanoscale interconnects |
| US9754883B1 (en) | 2016-03-04 | 2017-09-05 | International Business Machines Corporation | Hybrid metal interconnects with a bamboo grain microstructure |
| US9865538B2 (en) | 2016-03-09 | 2018-01-09 | International Business Machines Corporation | Metallic blocking layer for reliable interconnects and contacts |
| US9837350B2 (en) | 2016-04-12 | 2017-12-05 | International Business Machines Corporation | Semiconductor interconnect structure with double conductors |
| KR102654482B1 (ko) * | 2016-12-06 | 2024-04-03 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
| US10453749B2 (en) * | 2017-02-14 | 2019-10-22 | Tokyo Electron Limited | Method of forming a self-aligned contact using selective SiO2 deposition |
| WO2018163020A1 (ja) * | 2017-03-10 | 2018-09-13 | 株式会社半導体エネルギー研究所 | 導電体、導電体の作製方法、半導体装置、および半導体装置の作製方法 |
| US10096769B2 (en) | 2017-03-10 | 2018-10-09 | International Business Machines Corporation | Bottom electrode for MRAM applications |
| US10515903B2 (en) * | 2018-05-18 | 2019-12-24 | International Business Machines Corporation | Selective CVD alignment-mark topography assist for non-volatile memory |
| US11004794B2 (en) * | 2018-06-27 | 2021-05-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Partial barrier free vias for cobalt-based interconnects and methods of fabrication thereof |
| US10910307B2 (en) * | 2018-11-02 | 2021-02-02 | International Business Machines Corporation | Back end of line metallization structure |
| US10840185B2 (en) * | 2019-03-05 | 2020-11-17 | Texas Instruments Incorporated | Semiconductor device with vias having a zinc-second metal-copper composite layer |
| US11004791B2 (en) * | 2019-04-12 | 2021-05-11 | Advanced Micro Devices, Inc. | Semiconductor chip with stacked conductor lines and air gaps |
| WO2021174415A1 (en) * | 2020-03-03 | 2021-09-10 | Yangtze Memory Technologies Co., Ltd. | Protection structures in semiconductor chips and methods for forming the same |
Family Cites Families (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1282018C (en) * | 1985-04-17 | 1991-03-26 | Akiho Ota | Biaxial-orientation blow-molded bottle-shaped container |
| US4980752A (en) * | 1986-12-29 | 1990-12-25 | Inmos Corporation | Transition metal clad interconnect for integrated circuits |
| US5300813A (en) | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
| US5739579A (en) * | 1992-06-29 | 1998-04-14 | Intel Corporation | Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections |
| JP3326698B2 (ja) * | 1993-03-19 | 2002-09-24 | 富士通株式会社 | 集積回路装置の製造方法 |
| US6285082B1 (en) | 1995-01-03 | 2001-09-04 | International Business Machines Corporation | Soft metal conductor |
| US5695810A (en) | 1996-11-20 | 1997-12-09 | Cornell Research Foundation, Inc. | Use of cobalt tungsten phosphide as a barrier material for copper metallization |
| US6069072A (en) | 1997-04-28 | 2000-05-30 | Texas Instruments Incorporated | CVD tin barrier layer for reduced electromigration of aluminum plugs |
| US6010960A (en) * | 1997-10-29 | 2000-01-04 | Advanced Micro Devices, Inc. | Method and system for providing an interconnect having reduced failure rates due to voids |
| US6303505B1 (en) | 1998-07-09 | 2001-10-16 | Advanced Micro Devices, Inc. | Copper interconnect with improved electromigration resistance |
| US6123825A (en) * | 1998-12-02 | 2000-09-26 | International Business Machines Corporation | Electromigration-resistant copper microstructure and process of making |
| JP4044236B2 (ja) * | 1999-03-11 | 2008-02-06 | 株式会社東芝 | 半導体装置の製造方法 |
| US6342733B1 (en) | 1999-07-27 | 2002-01-29 | International Business Machines Corporation | Reduced electromigration and stressed induced migration of Cu wires by surface coating |
| US7388289B1 (en) * | 1999-09-02 | 2008-06-17 | Micron Technology, Inc. | Local multilayered metallization |
| KR100321156B1 (ko) * | 1999-12-23 | 2002-03-18 | 박종섭 | 반도체 소자의 금속배선 형성방법 |
| US6319819B1 (en) | 2000-01-18 | 2001-11-20 | Advanced Micro Devices, Inc. | Process for passivating top interface of damascene-type Cu interconnect lines |
| US6383925B1 (en) | 2000-02-04 | 2002-05-07 | Advanced Micro Devices, Inc. | Method of improving adhesion of capping layers to cooper interconnects |
| US6506677B1 (en) | 2001-05-02 | 2003-01-14 | Advanced Micro Devices, Inc. | Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance |
| US6429128B1 (en) | 2001-07-12 | 2002-08-06 | Advanced Micro Devices, Inc. | Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface |
| US6764951B1 (en) | 2002-02-28 | 2004-07-20 | Advanced Micro Devices, Inc. | Method for forming nitride capped Cu lines with reduced hillock formation |
| US6797652B1 (en) | 2002-03-15 | 2004-09-28 | Advanced Micro Devices, Inc. | Copper damascene with low-k capping layer and improved electromigration reliability |
| US20030207558A1 (en) * | 2002-05-06 | 2003-11-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method forming copper containing semiconductor features to prevent thermally induced defects |
| US6818557B1 (en) | 2002-12-12 | 2004-11-16 | Advanced Micro Devices, Inc. | Method of forming SiC capped copper interconnects with reduced hillock formation and improved electromigration resistance |
| US6975032B2 (en) * | 2002-12-16 | 2005-12-13 | International Business Machines Corporation | Copper recess process with application to selective capping and electroless plating |
| DE10303925B4 (de) * | 2003-01-31 | 2007-06-06 | Advanced Micro Devices, Inc., Sunnyvale | Dielektrische Barrierenschicht für eine Kupfermetallisierungsschicht mit einer über die Dicke hinweg variierenden Siliziumkonzentration und Verfahren zu deren Herstellung |
| WO2004088745A1 (ja) * | 2003-03-28 | 2004-10-14 | Fujitsu Limited | 半導体装置 |
| US20050173799A1 (en) * | 2004-02-05 | 2005-08-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure and method for its fabricating |
| US6952052B1 (en) | 2004-03-30 | 2005-10-04 | Advanced Micro Devices, Inc. | Cu interconnects with composite barrier layers for wafer-to-wafer uniformity |
| JP2006165454A (ja) * | 2004-12-10 | 2006-06-22 | Sony Corp | 半導体装置の製造方法および半導体装置 |
| DE102005014748B4 (de) * | 2005-03-31 | 2007-02-08 | Advanced Micro Devices, Inc., Sunnyvale | Technik zum elektrochemischen Abscheiden einer Legierung mit chemischer Ordnung |
-
2006
- 2006-11-15 US US11/560,044 patent/US7569475B2/en not_active Expired - Fee Related
-
2007
- 2007-09-10 WO PCT/US2007/077975 patent/WO2008060745A1/en not_active Ceased
- 2007-09-10 KR KR1020097009408A patent/KR101154748B1/ko not_active Expired - Fee Related
- 2007-09-10 CN CNA200780041313XA patent/CN101536170A/zh active Pending
- 2007-09-10 EP EP07842115.3A patent/EP2095409A4/en not_active Withdrawn
- 2007-09-10 JP JP2009537248A patent/JP5274475B2/ja not_active Expired - Fee Related
-
2009
- 2009-08-03 US US12/534,478 patent/US8138083B2/en not_active Expired - Fee Related
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