JP5274475B2 - エレクトロマイグレーションに対する向上した信頼度を有する相互接続構造体及びその製造方法 - Google Patents

エレクトロマイグレーションに対する向上した信頼度を有する相互接続構造体及びその製造方法 Download PDF

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Publication number
JP5274475B2
JP5274475B2 JP2009537248A JP2009537248A JP5274475B2 JP 5274475 B2 JP5274475 B2 JP 5274475B2 JP 2009537248 A JP2009537248 A JP 2009537248A JP 2009537248 A JP2009537248 A JP 2009537248A JP 5274475 B2 JP5274475 B2 JP 5274475B2
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Prior art keywords
conductive
dielectric material
interconnect
interconnect structure
conductive region
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Expired - Fee Related
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JP2009537248A
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English (en)
Japanese (ja)
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JP2010519723A5 (enExample
JP2010519723A (ja
Inventor
ヤン、チーチャオ
ワン、ピンチュアン
ワン、ユンユー
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H10D64/011—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2009537248A 2006-11-15 2007-09-10 エレクトロマイグレーションに対する向上した信頼度を有する相互接続構造体及びその製造方法 Expired - Fee Related JP5274475B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/560,044 US7569475B2 (en) 2006-11-15 2006-11-15 Interconnect structure having enhanced electromigration reliability and a method of fabricating same
US11/560,044 2006-11-15
PCT/US2007/077975 WO2008060745A1 (en) 2006-11-15 2007-09-10 Interconnect structure having enhanced electromigration reliability and a method of fabricating same

Publications (3)

Publication Number Publication Date
JP2010519723A JP2010519723A (ja) 2010-06-03
JP2010519723A5 JP2010519723A5 (enExample) 2010-07-15
JP5274475B2 true JP5274475B2 (ja) 2013-08-28

Family

ID=39368439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009537248A Expired - Fee Related JP5274475B2 (ja) 2006-11-15 2007-09-10 エレクトロマイグレーションに対する向上した信頼度を有する相互接続構造体及びその製造方法

Country Status (6)

Country Link
US (2) US7569475B2 (enExample)
EP (1) EP2095409A4 (enExample)
JP (1) JP5274475B2 (enExample)
KR (1) KR101154748B1 (enExample)
CN (1) CN101536170A (enExample)
WO (1) WO2008060745A1 (enExample)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100200991A1 (en) * 2007-03-15 2010-08-12 Rohan Akolkar Dopant Enhanced Interconnect
US7777344B2 (en) * 2007-04-11 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Transitional interface between metal and dielectric in interconnect structures
US7956466B2 (en) * 2008-05-09 2011-06-07 International Business Machines Corporation Structure for interconnect structure containing various capping materials for electrical fuse and other related applications
US8772156B2 (en) * 2008-05-09 2014-07-08 International Business Machines Corporation Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications
US9024431B2 (en) 2009-10-29 2015-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die contact structure and method
US8487447B2 (en) 2011-05-19 2013-07-16 International Business Machines Corporation Semiconductor structure having offset passivation to reduce electromigration
US9029260B2 (en) * 2011-06-16 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Gap filling method for dual damascene process
FR2979751A1 (fr) * 2011-09-02 2013-03-08 St Microelectronics Crolles 2 Element metallique d'interconnexion dans une puce de circuit integre et procede de realisation
US8796853B2 (en) 2012-02-24 2014-08-05 International Business Machines Corporation Metallic capped interconnect structure with high electromigration resistance and low resistivity
US9190348B2 (en) 2012-05-30 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Scheme for connector site spacing and resulting structures
KR101985937B1 (ko) 2012-07-11 2019-06-05 삼성전자주식회사 반도체 장치 및 그 제조방법
US8835305B2 (en) 2012-07-31 2014-09-16 International Business Machines Corporation Method of fabricating a profile control in interconnect structures
US9659869B2 (en) * 2012-09-28 2017-05-23 Intel Corporation Forming barrier walls, capping, or alloys /compounds within metal lines
KR102057067B1 (ko) 2013-01-29 2019-12-18 삼성전자주식회사 반도체 장치의 배선 구조체 및 그 형성 방법
JP2015060918A (ja) * 2013-09-18 2015-03-30 株式会社東芝 半導体装置
US9362239B2 (en) * 2014-10-21 2016-06-07 Globalfoundries Inc. Vertical breakdown protection layer
US9431343B1 (en) * 2015-03-11 2016-08-30 Samsung Electronics Co., Ltd. Stacked damascene structures for microelectronic devices
US9418934B1 (en) 2015-06-30 2016-08-16 International Business Machines Corporation Structure and fabrication method for electromigration immortal nanoscale interconnects
US9754883B1 (en) 2016-03-04 2017-09-05 International Business Machines Corporation Hybrid metal interconnects with a bamboo grain microstructure
US9865538B2 (en) 2016-03-09 2018-01-09 International Business Machines Corporation Metallic blocking layer for reliable interconnects and contacts
US9837350B2 (en) 2016-04-12 2017-12-05 International Business Machines Corporation Semiconductor interconnect structure with double conductors
KR102654482B1 (ko) * 2016-12-06 2024-04-03 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10453749B2 (en) * 2017-02-14 2019-10-22 Tokyo Electron Limited Method of forming a self-aligned contact using selective SiO2 deposition
WO2018163020A1 (ja) * 2017-03-10 2018-09-13 株式会社半導体エネルギー研究所 導電体、導電体の作製方法、半導体装置、および半導体装置の作製方法
US10096769B2 (en) 2017-03-10 2018-10-09 International Business Machines Corporation Bottom electrode for MRAM applications
US10515903B2 (en) * 2018-05-18 2019-12-24 International Business Machines Corporation Selective CVD alignment-mark topography assist for non-volatile memory
US11004794B2 (en) * 2018-06-27 2021-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Partial barrier free vias for cobalt-based interconnects and methods of fabrication thereof
US10910307B2 (en) * 2018-11-02 2021-02-02 International Business Machines Corporation Back end of line metallization structure
US10840185B2 (en) * 2019-03-05 2020-11-17 Texas Instruments Incorporated Semiconductor device with vias having a zinc-second metal-copper composite layer
US11004791B2 (en) * 2019-04-12 2021-05-11 Advanced Micro Devices, Inc. Semiconductor chip with stacked conductor lines and air gaps
WO2021174415A1 (en) * 2020-03-03 2021-09-10 Yangtze Memory Technologies Co., Ltd. Protection structures in semiconductor chips and methods for forming the same

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1282018C (en) * 1985-04-17 1991-03-26 Akiho Ota Biaxial-orientation blow-molded bottle-shaped container
US4980752A (en) * 1986-12-29 1990-12-25 Inmos Corporation Transition metal clad interconnect for integrated circuits
US5300813A (en) 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
JP3326698B2 (ja) * 1993-03-19 2002-09-24 富士通株式会社 集積回路装置の製造方法
US6285082B1 (en) 1995-01-03 2001-09-04 International Business Machines Corporation Soft metal conductor
US5695810A (en) 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
US6069072A (en) 1997-04-28 2000-05-30 Texas Instruments Incorporated CVD tin barrier layer for reduced electromigration of aluminum plugs
US6010960A (en) * 1997-10-29 2000-01-04 Advanced Micro Devices, Inc. Method and system for providing an interconnect having reduced failure rates due to voids
US6303505B1 (en) 1998-07-09 2001-10-16 Advanced Micro Devices, Inc. Copper interconnect with improved electromigration resistance
US6123825A (en) * 1998-12-02 2000-09-26 International Business Machines Corporation Electromigration-resistant copper microstructure and process of making
JP4044236B2 (ja) * 1999-03-11 2008-02-06 株式会社東芝 半導体装置の製造方法
US6342733B1 (en) 1999-07-27 2002-01-29 International Business Machines Corporation Reduced electromigration and stressed induced migration of Cu wires by surface coating
US7388289B1 (en) * 1999-09-02 2008-06-17 Micron Technology, Inc. Local multilayered metallization
KR100321156B1 (ko) * 1999-12-23 2002-03-18 박종섭 반도체 소자의 금속배선 형성방법
US6319819B1 (en) 2000-01-18 2001-11-20 Advanced Micro Devices, Inc. Process for passivating top interface of damascene-type Cu interconnect lines
US6383925B1 (en) 2000-02-04 2002-05-07 Advanced Micro Devices, Inc. Method of improving adhesion of capping layers to cooper interconnects
US6506677B1 (en) 2001-05-02 2003-01-14 Advanced Micro Devices, Inc. Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance
US6429128B1 (en) 2001-07-12 2002-08-06 Advanced Micro Devices, Inc. Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface
US6764951B1 (en) 2002-02-28 2004-07-20 Advanced Micro Devices, Inc. Method for forming nitride capped Cu lines with reduced hillock formation
US6797652B1 (en) 2002-03-15 2004-09-28 Advanced Micro Devices, Inc. Copper damascene with low-k capping layer and improved electromigration reliability
US20030207558A1 (en) * 2002-05-06 2003-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method forming copper containing semiconductor features to prevent thermally induced defects
US6818557B1 (en) 2002-12-12 2004-11-16 Advanced Micro Devices, Inc. Method of forming SiC capped copper interconnects with reduced hillock formation and improved electromigration resistance
US6975032B2 (en) * 2002-12-16 2005-12-13 International Business Machines Corporation Copper recess process with application to selective capping and electroless plating
DE10303925B4 (de) * 2003-01-31 2007-06-06 Advanced Micro Devices, Inc., Sunnyvale Dielektrische Barrierenschicht für eine Kupfermetallisierungsschicht mit einer über die Dicke hinweg variierenden Siliziumkonzentration und Verfahren zu deren Herstellung
WO2004088745A1 (ja) * 2003-03-28 2004-10-14 Fujitsu Limited 半導体装置
US20050173799A1 (en) * 2004-02-05 2005-08-11 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure and method for its fabricating
US6952052B1 (en) 2004-03-30 2005-10-04 Advanced Micro Devices, Inc. Cu interconnects with composite barrier layers for wafer-to-wafer uniformity
JP2006165454A (ja) * 2004-12-10 2006-06-22 Sony Corp 半導体装置の製造方法および半導体装置
DE102005014748B4 (de) * 2005-03-31 2007-02-08 Advanced Micro Devices, Inc., Sunnyvale Technik zum elektrochemischen Abscheiden einer Legierung mit chemischer Ordnung

Also Published As

Publication number Publication date
EP2095409A1 (en) 2009-09-02
US20080111239A1 (en) 2008-05-15
CN101536170A (zh) 2009-09-16
EP2095409A4 (en) 2014-05-21
KR20090080514A (ko) 2009-07-24
US20090289368A1 (en) 2009-11-26
JP2010519723A (ja) 2010-06-03
WO2008060745A1 (en) 2008-05-22
US8138083B2 (en) 2012-03-20
US7569475B2 (en) 2009-08-04
KR101154748B1 (ko) 2012-06-08

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