Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
  • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
• • H10D64/011—
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5226—Via connections in a multilevel interconnection structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/528—Layout of the interconnection structure
  • H01L23/5283—Cross-sectional geometry
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L23/53204—Conductive materials
  • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
  • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
  • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L23/53204—Conductive materials
  • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
  • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
  • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L23/5329—Insulating materials
  • H01L23/53295—Stacked insulating layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates to a semiconductor interconnect structure, and a method of fabricating the same. More particularly, the present invention relates to a semiconductor interconnect structure having enhanced electromigration (EM) reliability in which an EM preventing liner is present within a conductive feature of a dielectric material.
• EM electromigration
• semiconductor devices include a plurality of circuits which form an integrated circuit (IC) fabricated on a semiconductor substrate.
• IC integrated circuit
• a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures.
• the wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
• metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as "crosstalk") are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
• crosstalk Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as "crosstalk") are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
• EM electromigration
• VLSI very large scale integrated
• metal atoms such as Cu atoms
• the EM initial voids first nucleate at the metal/dielectric cap interface and then grow in the direction of the bottom of the interconnect, which eventually results in a circuit dead opening.
• FIGS. 1A-1D are pictorial representations of a prior art interconnect structure at various stages of an EM failure.
• reference numeral 12 denotes the dielectric cap
• reference numeral 10 denotes the metal interconnect feature; all other components of the prior art interconnect structure are not labeled to avoid obscuring the EM problem.
• FIG. IA is at an initial stress stage.
• FIG. IB is at a time when void 14 nucleation initiates at the metal interconnect feature 10/dielectric cap 12 interface.
• FIG. 1C is at a time when the void 14 grows toward the bottom of the conductive feature 10
• FIG. ID is at a time in which the void 14 growth crosses the metal interconnect feature 10 causing a circuit dead opening.
• FIGS. 2A-2B are SEM images from a stressed interconnect structure and they illustrate a void forming in the metal line (M2), which implies the mass transport in the metal line occurred along the interface of the metal line and the overlying dielectric cap.
• M2 metal line
• the present invention relates to an interconnect structure having improved EM reliability.
• the inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating an EM preventing liner within a metal interconnect.
• Other benefits of the inventive structure include: prevention of sudden data loss and enhancement of the lifetime of the semiconductor product.
• the semiconductor interconnect structure of the present invention comprises:
• a dielectric material having at least one conductively filled feature located therein, wherein said at least one conductively filled feature includes an electromigration (EM) preventing liner that at least partially separates a first conductive region of said at least one conductively filled feature from a second conductive region of said at least one conductively filled feature.
• EM electromigration
• a "U-shaped" EM preventing liner is provided that abuts a diffusion barrier that separates the at least one conductively filled feature from the dielectric material.
• a space is located between the "U-shaped" EM preventing liner and the diffusion barrier.
• a horizontal EM liner that abuts the diffusion barrier is provided.
• a space exists between the horizontal EM liner and the diffusion barrier.
• Another aspect of the present invention relates to a method of fabricating the inventive interconnect structure.
• the inventive method includes the steps of: providing at least one opening in a dielectric material, said at least one opening is lined with a diffusion barrier;
• a first conductive region within said at least one opening; forming an electromigration (EM) preventing liner on at least a surface of said first conductive region; and
• EM electromigration
• a "U-shaped" EM preventing liner is provided that abuts the diffusion barrier that separates the conductive feature from the dielectric material.
• a space is located between the "U-shaped" EM preventing liner and the diffusion barrier.
• a horizontal EM liner that abuts the diffusion barrier is provided.
• a space exists between the horizontal EM liner and the diffusion barrier.
• FIGS. 1 A-ID are pictorial representations (through cross sectional views) illustrating the formation of a circuit dead opening in a prior art interconnect structure which is caused by EM failure.
• FIGS. 2A-2B are SEM images illustrating the formation of a circuit dead opening in a prior art interconnect structure caused by EM failure.
• FIGS. 3A-3D are pictorial representations (through cross sectional views) of various interconnect structure of the present invention in which a circuit dead opening is avoided by forming an EM preventing liner within the metal feature.
• FIGS. 4A-4F are pictorial representations (through cross sectional views) illustrating the basic processing steps that are employed in forming the structure shown in FIG. 3 A.
• FIG. 5 is a pictorial representation (through a cross sectional view) of an intermediate structure that is used in forming the structure shown in FIG. 3C.
• FIG. 6 is pictorial representation (through a cross sectional view) depicting a non- ideal bottom-up deposition process used in partially filling at least one opening of a dielectric material.
• the present invention provides an interconnect structure having improved EM reliability.
• the inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating an EM preventing liner within a metal interconnect.
• FIGS. 3A-3D illustrate various embodiments of the present invention. Specifically, FIG. 3A-3D illustrate interconnect structures of the present invention in which the EM preventing liner 66 is located within an opening of a dielectric material 54B which is filled with conductive material 64 and 68.
• the conductive material 64 forms a first conductive region
• conductive material 68 forms a second conductive region within second dielectric material 54B.
• the first and second conductive regions in turn form a conductive feature within the second dielectric material 54B.
• FIG. 3A illustrates a first embodiment of the present invention in which a "U-shaped" EM preventing liner 66 abuts the diffusion barrier 58' that separates conductive materials 64 and 68 from the dielectric material 54B.
• FIG. 3B illustrates a second embodiment in which a space is located between the "U-shaped" EM preventing liner 66 and the diffusion barrier 58'.
• FIG. 3C illustrates a third embodiment in which a horizontal EM liner 66 abuts the diffusion barrier
• FIG. 3D illustrates a fourth embodiment of the present invention in which a space exists between the horizontal EM liner 66 and the diffusion barrier 58'.
• FIGS. 4A-4F illustrate the basic processing steps that are used in forming the semiconductor interconnect structure shown in FIG. 3A.
• the "U-shaped" EM preventing liner 66 abuts the diffusion barrier 58' that lines the at least one opening of a second dielectric material 54B.
• the inventive method begins with providing the patterned interconnect structure 50 shown in FIG. 4 A.
• the patterned interconnect structure 50 shown in FIG. 4A comprises a first interconnect level 52A and a second interconnect level 52B that are separated in part by a dielectric capping layer 60.
• the first interconnect level 52A which may be located above a semiconductor substrate including one or more semiconductor devices, comprises a first dielectric material 54A having at least one conductive feature 56 that is separated from the first dielectric material 54A by a diffusion barrier 58.
• the second interconnect level 52B comprises a second dielectric material 54B' having at least one opening located therein.
• FIG. 4A there are shown a line opening 62A for a single damascene structure, and a via opening 63A and a line opening 63B for a dual damascene structure in the second dielectric material 54B. Although these various openings are shown, the present invention works in cases in which only a single damascene line opening is formed or damascene line and via openings are formed. When dual damascene line and via openings are formed, part of the dielectric capping layer 60 located above the at least one conductive feature 56 is removed.
• the patterned interconnect structure 50 also includes a diffusion barrier 58'within the at least one opening that is formed in the second dielectric material 54B.
• the patterned interconnect structure 50 shown in FIG. 4A is fabricated utilizing standard back-end-of-the-line (BEOL) processes that are well known in the art including a single damascene or dual damascene process.
• BEOL back-end-of-the-line
• a first via then line opening process may be used, or a first line then via opening process may be used.
• the process typically includes deposition, lithography, etching and filling of an opening with a diffusion barrier and then a conductive material, and thereafter planarization.
• the processing details for fabricating such an interconnect structure are well known to those skilled in the art, the details are omitted herein to avoid obscuring of the current invention.
• the first interconnect level 52A of the patterned interconnect structure 50 may be formed atop a substrate (not shown in the drawings of the present application).
• the substrate which is not shown, may comprise a semiconducting material, an insulating material, a conductive material or any combination thereof.
• the substrate is comprised of a semiconducting material
• any semiconductor such as Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, InP and other III/V or II/VI compound semiconductors may be used.
• the present invention also contemplates cases in which the semiconductor substrate is a layered semiconductor such as, for example, Si/SiGe, Si/SiC, silicon-on-insulators (SOIs) or silicon germanium-on-insulators (SGOIs).
• the insulating material can be an organic insulator, an inorganic insulator or a combination thereof including multilayers.
• the substrate may include, for example, polySi, an elemental metal, alloys of elemental metals, a metal suicide, a metal nitride or combinations thereof, including multilayers.
• the substrate comprises a semiconducting material, one or more semiconductor devices such as, for example, complementary metal oxide semiconductor (CMOS) devices can be fabricated thereon.
• CMOS complementary metal oxide semiconductor
• the substrate may represent a first interconnect level of a multilayered interconnect structure.
• the first dielectric material 54A and the second dielectric material 54B comprise any interlevel or intralevel dielectric including inorganic dielectrics or organic dielectrics.
• the first and second dielectric materials 54 A and 54B respectively may be porous or non-porous.
• suitable dielectrics that can be used as the first and second dielectric materials 54A and 54B include, but are not limited to: SiO 2 , silsesquioxanes, C doped oxides (i.e., organosilicates) that include atoms of Si, C, O and H, thermosetting polyarylene ethers, or multilayers thereof.
• the term "polyarylene” is used in this application to denote aryl moieties or inertly substituted aryl moieties which are linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl and the like.
• the first and second dielectric materials 54A and 54B typically have a dielectric constant that is about 4.0 or less, with a dielectric constant of about 2.8 or less being even more typical. All dielectric constants mentioned herein are relative to a vacuum, unless otherwise noted. These dielectrics generally have a lower parasitic cross talk as compared with dielectric materials that have a higher dielectric constant than 4.0.
• the thickness of the dielectric materials may vary depending upon the dielectric material used as well as the exact number of dielectrics layers within the first and second dielectric materials. Typically, and for normal interconnect structures, the first dielectric material 54A and second dielectric material 54B each have a thickness from about 50 to about 1000 nm.
• the diffusion barriers 58 and 58' which may be the same or different materials, comprise Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, WN or any other material that can serve as a barrier to prevent conductive material from diffusing there through.
• the thickness of the diffusion barriers 58 and 58' may vary depending on the deposition process used as well as the material employed. Typically, the diffusion barriers 58 and 58' each have a thickness from about 4 to about 40 nm, with a thickness from about 7 to about 20 nm being more typical.
• the conductive material used in forming the conductive feature 56 includes, for example, polySi, a conductive metal, an alloy comprising at least one conductive metal, a conductive metal suicide or combinations thereof.
• the conductive material that is used in forming the at least one conductive feature 56 is a conductive metal such as Cu, W or Al, with Cu or a Cu alloy (such as AlCu) being highly preferred in the present invention.
• the dielectric capping layer 60 which separates, at least in part, the second interconnect level 52B from the first interconnect level 52A comprises any suitable dielectric capping material such as, for example, SiC, Si 4 NH 3 , SiO 2 , a carbon doped oxide, a nitrogen and hydrogen doped silicon carbide SiC(N 5 H) or multilayers thereof.
• the thickness of the dielectric capping layer 60 may vary depending on the technique used to form the same as well as the material make-up of the layer. Typically, the dielectric capping layer 60 has a thickness from about 15 to about 100 nm, with a thickness from about 25 to about 45 nm being more typical.
• a conductive material 64 (forming a first conductive region of the upper interconnect level 52B) is partially formed within the at least one opening (via and/or line openings) in the second dielectric material 54B.
• the conductive material 64 may comprise the same or different conductive material as defined above for the at least one conductive feature 56.
• the conductive material 64 is Cu, W or Al, with Cu or a Cu alloy (such as AlCu) being more preferred in the present invention.
• the conductive material 64 may be formed by partially filling the at least one opening in the second dielectric material 54B or by fully filling the at least one opening and then recessing the conductive material to a level below the upper surface of the second dielectric material 54B.
• Any conventional deposition process including chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, chemical solution deposition or plating that fills the at least one opening from the bottom upwards can be used.
• CVD chemical vapor deposition
• PECVD plasma enhanced chemical vapor deposition
• sputtering chemical solution deposition
• plating chemical solution deposition or plating that fills the at least one opening from the bottom upwards
• a bottom-up plating process is employed.
• an etching process that selectively removes portions of the conductive material 64 is used to provide partial filling of the at least one opening in the second dielectric material 54B. It is noted that in FIG. 4B, an ideal bottom-up fill is shown. By “ideal', it is meant that the fill occurs mainly from the lower portion of the opening upwards.
• FIG. 4C illustrates the structure after an EM preventing liner 66 is formed on all the exposed surfaces (including horizontal and vertical) of the structure shown in FIG. 4B.
• the EM preventing liner 66 comprises Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Ir, IrCu, Co(W,B,P,Mo,Re) or any like material that can prevent EM failure.
• the EM preventing liner 66 is formed utilizing a non-directional deposition process such as, for example, CVD and sputtering.
• the EM preventing liner 66 typically has a thickness from about 1 to about 20 nm, with a thickness from about 2 to about 8 nm being more typical.
• the EM preventing liner 66 can be formed utilizing a directional deposition process that selectively deposits the EM preventing liner only one horizontal surfaces of the structure.
• This embodiment of the present invention is shown, for example, in FIG. 5. It is noted that this embodiment of the present invention, also includes a catalytic plating process in which the EM preventing liner 66 is only formed on the exposed horizontal surfaces of the conductive material 64. In such an embodiment (not shown), no EM preventing liner is formed on the second dielectric material 64B.
• the directional deposition of the EM preventing liner 66 is used in forming the interconnect structures shown, for example, in FIGS. 3C and 3D, i.e., horizontal EM preventing liners within the conductively filled openings of the second dielectric material 54B.
• additional conductive material 68 which may comprise the same or different, preferably the same, conductor as conductive material 64 is formed. Any conventional deposition process can be used in forming the structure shown in FIG. 4D. It is noted that the conductive material 68 forms a second conductive region of the upper interconnect level 52B.
• FIG. 4E illustrates the structure after planarizing the additional conductive material 68 such that an upper surface thereof is substantially co-planar to an upper surface of the second dielectric material 54B. It is noted that during this planarization step any EM preventing liner located atop the second dielectric material 54B is removed. Planarization may be achieved by chemical mechanical polishing and/or grinding. [0046] After planarization, a second dielectric capping layer 60' is formed on the structure shown in FIG. 4E so as to provide the structure shown in FIG. 3A. The second dielectric capping layer 60' may be comprised of the same or different material as the first dielectric capping layer 60.
• non-ideal deposition of the conductive material 64 occurs when partially filling the at least one opening in the second dielectric material 54B.
• This embodiment of begins by first providing the patterned interconnect structure 50 illustrated in FIG. 4A.
• non-ideal deposition of the conductive material 64 occurs providing the structure shown, for example, in FIG. 6.
• portions of the at least one opening that are in proximity to the patterned vertical walls of the second dielectric material 54B also include the conductive material 64.
• this embodiment is not an ideal bottom-up deposition. This non-ideal deposition occurs in most cases.
• the present invention provides an interconnect structure having improved EM reliability by incorporating an EM preventing liner within a metal interconnect.
• Other benefits of the inventive structure include: prevention of sudden data loss and enhancement of the lifetime of the semiconductor product.
• inventive interconnect structure is that a weak interface between the conductive feature in the second dielectric material 54B and the overlying dielectric capping layer 60' is avoided. Also, the inventive structure is capable of modulating stress better than prior art interconnect structures.
• the present invention finds industrial applicability in the fabrication of semiconductor structures, and more particularly, in the field of design and manufacture of devices and circuit integral to VLSI chips.

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