JP2010171092A5 - - Google Patents

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Publication number
JP2010171092A5
JP2010171092A5 JP2009010499A JP2009010499A JP2010171092A5 JP 2010171092 A5 JP2010171092 A5 JP 2010171092A5 JP 2009010499 A JP2009010499 A JP 2009010499A JP 2009010499 A JP2009010499 A JP 2009010499A JP 2010171092 A5 JP2010171092 A5 JP 2010171092A5
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JP
Japan
Prior art keywords
lsi
clock signal
flip
flops
circuit
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Application number
JP2009010499A
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English (en)
Japanese (ja)
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JP2010171092A (ja
JP5070228B2 (ja
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Priority to JP2009010499A priority Critical patent/JP5070228B2/ja
Priority claimed from JP2009010499A external-priority patent/JP5070228B2/ja
Priority to US12/690,659 priority patent/US7994822B2/en
Publication of JP2010171092A publication Critical patent/JP2010171092A/ja
Publication of JP2010171092A5 publication Critical patent/JP2010171092A5/ja
Application granted granted Critical
Publication of JP5070228B2 publication Critical patent/JP5070228B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009010499A 2009-01-21 2009-01-21 半導体装置 Expired - Fee Related JP5070228B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009010499A JP5070228B2 (ja) 2009-01-21 2009-01-21 半導体装置
US12/690,659 US7994822B2 (en) 2009-01-21 2010-01-20 Semiconductor device for synchronous communication between stacked LSI

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009010499A JP5070228B2 (ja) 2009-01-21 2009-01-21 半導体装置

Publications (3)

Publication Number Publication Date
JP2010171092A JP2010171092A (ja) 2010-08-05
JP2010171092A5 true JP2010171092A5 (enExample) 2011-10-20
JP5070228B2 JP5070228B2 (ja) 2012-11-07

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Family Applications (1)

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JP2009010499A Expired - Fee Related JP5070228B2 (ja) 2009-01-21 2009-01-21 半導体装置

Country Status (2)

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US (1) US7994822B2 (enExample)
JP (1) JP5070228B2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8179173B2 (en) * 2010-03-12 2012-05-15 Raytheon Company Digitally calibrated high speed clock distribution
US8384435B2 (en) * 2011-01-05 2013-02-26 Texas Instruments Incorporated Clock switching circuit with priority multiplexer
JP5643665B2 (ja) * 2011-01-24 2014-12-17 学校法人慶應義塾 積層型半導体集積回路装置
JP5643673B2 (ja) * 2011-02-16 2014-12-17 学校法人慶應義塾 電子回路
US8786080B2 (en) * 2011-03-11 2014-07-22 Altera Corporation Systems including an I/O stack and methods for fabricating such systems
JP5807550B2 (ja) 2012-01-10 2015-11-10 株式会社ソシオネクスト 半導体装置
JP6312377B2 (ja) * 2013-07-12 2018-04-18 キヤノン株式会社 半導体装置
US9231603B2 (en) 2014-03-31 2016-01-05 International Business Machines Corporation Distributed phase detection for clock synchronization in multi-layer 3D stacks
KR20150141018A (ko) * 2014-06-09 2015-12-17 에스케이하이닉스 주식회사 관통 비아를 통해 연결되는 적층 반도체 장치 및 모니터링 방법
US10147658B2 (en) 2014-06-09 2018-12-04 SK Hynix Inc. Stacked semiconductor apparatus being electrically connected through through-via and monitoring method
US9319829B1 (en) * 2014-10-30 2016-04-19 Hua Wen Hsu Wireless inductive pointer clock
JP2017163204A (ja) * 2016-03-07 2017-09-14 ＡＰＲＥＳＩＡ Ｓｙｓｔｅｍｓ株式会社 通信装置
KR102605617B1 (ko) 2016-11-10 2023-11-23 삼성전자주식회사 적층 반도체 패키지
KR20230071383A (ko) 2021-11-16 2023-05-23 삼성전자주식회사 반도체 장치, 반도체 패키지 및 메모리 시스템

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4063392B2 (ja) * 1998-03-26 2008-03-19 富士通株式会社 信号伝送システム
JP3475857B2 (ja) * 1999-06-03 2003-12-10 日本電気株式会社 ソースシンクロナス転送方式
JP2001251283A (ja) * 2000-03-06 2001-09-14 Hitachi Ltd インターフェース回路
US6331800B1 (en) * 2000-07-21 2001-12-18 Hewlett-Packard Company Post-silicon methods for adjusting the rise/fall times of clock edges
JP4752369B2 (ja) * 2004-08-24 2011-08-17 ソニー株式会社 半導体装置および基板
JP5063958B2 (ja) 2006-08-18 2012-10-31 川崎マイクロエレクトロニクス株式会社 半導体集積回路および半導体集積回路の設計方法
JP5149554B2 (ja) 2007-07-17 2013-02-20 株式会社日立製作所 半導体装置
JP2009032857A (ja) 2007-07-26 2009-02-12 Hitachi Ltd 半導体集積回路および半導体装置
US8781053B2 (en) * 2007-12-14 2014-07-15 Conversant Intellectual Property Management Incorporated Clock reproducing and timing method in a system having a plurality of devices
JP5258343B2 (ja) 2008-03-27 2013-08-07 ルネサスエレクトロニクス株式会社 半導体装置及び半導体集積回路

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