WO2019052243A1 - 接口单元以及具有该接口单元的接口模块和芯片 - Google Patents

接口单元以及具有该接口单元的接口模块和芯片 Download PDF

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Publication number
WO2019052243A1
WO2019052243A1 PCT/CN2018/091467 CN2018091467W WO2019052243A1 WO 2019052243 A1 WO2019052243 A1 WO 2019052243A1 CN 2018091467 W CN2018091467 W CN 2018091467W WO 2019052243 A1 WO2019052243 A1 WO 2019052243A1
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Prior art keywords
input
output
interface unit
flip
flop
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PCT/CN2018/091467
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English (en)
French (fr)
Inventor
信恒超
季秉武
周昔平
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华为技术有限公司
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Publication of WO2019052243A1 publication Critical patent/WO2019052243A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5381—Crossover interconnections, e.g. bridge stepovers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present application relates to the field of integrated circuit technologies, and in particular, to an interface unit and an interface module and a chip having the interface unit.
  • the chip package usually integrates multiple bare chips (DIE) into a complete chip through specific methods and other components.
  • the main packaging methods are through silicon via (TSV) and multi-chip package technology (multi Chip package, MCP).
  • TSV refers to a packaging method for realizing signal connection between different layers in the chip by means of perforation
  • MCP multi-chip package technology
  • FIG. 1a A schematic diagram of a longitudinal section of a chip obtained by using a TSV package is shown in FIG. 1a.
  • a microbump 901 and a silicon interposer are sequentially laminated between a die and a package substrate 900.
  • Interposer) 902 and controlled collapsed chip connection bump (C4 bump) 903 the interconnection of signals between DIEs is realized by microbumps and silicon interposer.
  • the DIE is directly connected to the C4 bump to implement interconnection of signals between DIEs in the package substrate.
  • the spacing required for routing in the package substrate is much larger than the spacing of the traces in the silicon interposer.
  • the two package methods have different requirements on the trace density on the bare chip.
  • the TSV package requires a high trace density of the DIE
  • the MCM package requires a low trace density of the DIE. Since the trace density of the two packages is different, it is necessary to make the chips obtained by the two packages have the same bandwidth when used, so that the number of pins and the transfer rate are different. Therefore, when different packaging modes are adopted, different output interface units capable of forming a specific trace density are configured for the DIE to be connected with corresponding input interface units to realize interconnection of data signals between DIEs.
  • the circuit of the output interface unit and the corresponding input interface unit in the TSV packaging method is as shown in FIG. 1b.
  • FIG. 1b when the TSV package is used for packaging, each output interface unit and the corresponding input interface unit are required. Two data signal transmission ends and one clock signal transmission end.
  • FIG. 2 The circuit of the output interface unit and the corresponding input interface unit in the MCM package method is shown in FIG. 2.
  • FIG. 2 when the MCM package method is used, if the bandwidth is the same as that of the TSV package, each The output interface unit and the corresponding input interface unit only require one data signal transmission end and one clock signal transmission end.
  • the present application provides an interface unit and an interface module and a chip having the same, to solve the problem that the TSV and MCM packaging methods cannot adopt the same form of interface unit.
  • the present application provides the following aspects:
  • the present application provides an output interface unit including a first D flip-flop, a second D flip-flop, a splitter, a first multiplexer, and a second multiplexer.
  • An input of the splitter is coupled to an output of the first D flip-flop.
  • a second output of the splitter is coupled to a first input of the first multiplexer.
  • the output ends of the second D flip-flops are respectively connected to the second input end of the first multiplexer and the second input end of the second multiplexer.
  • An output of the first multiplexer is coupled to a first input of the second multiplexer.
  • the first output of the splitter is a first output of the output interface unit.
  • the output of the second multiplexer is the second output of the output interface selection module.
  • the second output of the splitter and the first input of the second multiplexer are controlled by the same routing signal.
  • the output interface unit further includes a first controller, where the first controller is configured to provide a first routing signal.
  • the signal value of the first routing signal includes a first signal value or a second signal value.
  • the first signal value is used to clamp the second output of the splitter and the first input of the second multiplexer.
  • the second signal value is used to clamp the first output of the splitter and the second input of the second multiplexer.
  • the second output of the splitter and the first input of the second multiplexer are clamped.
  • the splitter outputs a signal through a second output.
  • the second multiplexer selects a signal input by the first input as an input signal.
  • the signal value of the first routing signal is the second signal value
  • the first output of the splitter and the second input of the second multiplexer are clamped.
  • the splitter outputs a signal through the first output.
  • the second multiplexer selects a signal input by the second input as an input signal.
  • the output interface unit further includes a first clock generator.
  • the first multiplexer selects a signal input by the first input as an input signal or a signal input by the second input as an input signal according to a clock signal generated by the first clock generator.
  • the output interface unit is provided with a splitter, a multiplexer and a controller for providing a routing signal
  • the signal value of the routing signal can be controlled according to the packaging manner, thereby controlling the output state of the splitter and The input state of the multiplexer, which in turn controls the output state of the first output of the output interface unit, such that the output interface unit can be used when any of the TSV and MCM packages are employed.
  • the output interface unit and the corresponding input interface unit may be packaged in a TSV manner, and the output interface unit transmits data on a rising edge of the transmitting end clock (TX clock), and the input interface unit is at the receiving end clock (RX clock). The falling edge receives data.
  • the RX clock is the associated clock of the TX clock.
  • the receiving end of the input interface unit shapes the associated clock with a digital phase-locked loop (DLL).
  • the DLL is used to generate a 180° phase difference between the associated clock and the received clock. Under this associated clock, the data signal sent by the transmitting end is center sampled. Thereby reducing the dependence on the clock duty cycle, increasing the margin of data sampling/timing margin.
  • the waveform is shown in Figure 3b.
  • the output interface unit and the corresponding input interface unit may be encapsulated in an MCM manner, and the transmitting end of the output interface unit shapes the input clock into a clock with an appropriate duty ratio through a DLL.
  • the data is transmitted using the 0°, 180° phase clock generated by the DLL, and each bit transmits 1 bit of data.
  • the receiving end of the corresponding input interface unit is processed by the DLL from the transmitting end to generate a 90° and 270° phase clock. That is, the associated clock forms a phase difference of 90° and 270° with the received clock, and then the center signal is sampled by the data signal transmitted from the transmitting end under the phase clock. Its waveform is shown in Figure 3c.
  • the output interface unit provided by the present application does not need to change the circuit of the interface unit, and only by controlling the signal value of the routing signal, it is possible to select to transmit data by double rate (ie, MCM mode encapsulation), or The data is selected to be transmitted at a single rate (ie, TSV mode), that is, the output interface unit can be used when any of the TSV and MCM packages are employed.
  • the output interface unit further includes a first clock generator.
  • the first D flip-flop is the same as the second D flip-flop clock.
  • the first D flip-flop is synchronized with the second D flip-flop.
  • the first multiplexer selects a signal input by the first input terminal or a signal input by the second input terminal as an input signal according to a clock signal generated by the first clock generator.
  • the output of the first clock generator is the clock output of the output interface unit.
  • the application further provides an output interface module comprising at least one output interface unit of the first aspect.
  • clocks of all output interface units in the output interface module are the same. All of the output interface units are synchronized.
  • all output interface units in the output interface module share a clock generator.
  • all of the output interface units in the output interface module are controlled by the same routing signal. All of the output interface units can be made to use the same package.
  • all output interface units in the output interface module share one controller.
  • the present application further provides a chip, including a first internal processing unit and at least one output interface unit according to the first aspect, wherein the first internal processing unit is used for DIE internal information processing, the output The input end of the interface unit is connected to the output corresponding to the first internal processing unit.
  • the clocks of all the output interface units in the chip are the same. All of the output interface units in the chip are synchronized.
  • all of the output interface units in the chip are controlled by the same routing signal. All of the output interface units can be made to use the same package.
  • the chip comprises a first internal processing unit and at least one output interface module of the second aspect.
  • An input end of the output interface unit of the output interface module is connected to an output end corresponding to the first internal processing unit.
  • the clocks of all the output interface modules in the chip are the same. All of the output interface modules are synchronized.
  • all of the output interface modules in the chip are controlled by the same routing signal. All the output interface modules can be made in the same package.
  • the present application further provides an input interface unit, including a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, and a third multiplexer.
  • An output of the third D flip-flop is coupled to a first input of the third multiplexer.
  • An output of the fourth D flip-flop is coupled to a second input of the third multiplexer.
  • the input end of the third D flip-flop is a first input end of the output interface unit.
  • the input end of the fourth D flip-flop or the input end of the fifth D flip-flop is a second input end of the output interface unit.
  • the output of the third multiplexer is the first output of the output interface unit.
  • the output end of the fifth D flip-flop is a second output end of the output interface unit.
  • the fourth flip flop is a falling edge flip flop.
  • the input interface unit further includes a second controller.
  • the second controller is configured to provide a second routing signal.
  • the signal value of the second routing signal includes a third signal value and a fourth signal value.
  • the third signal value is used to clamp the second input of the third multiplexer.
  • the fourth signal value is used to clamp the first input of the third multiplexer.
  • the second input of the third multiplexer is clamped.
  • the third multiplexer selects a signal input by the first input as an input signal.
  • the signal value of the second routing signal is the fourth signal value
  • the first input of the third multiplexer is clamped.
  • the third multiplexer selects a signal input by the second input as an input signal.
  • the input interface unit also includes a second clock generator. If the signal value of the second routing signal is the third signal value, the clock generated by the second clock generator has a phase difference of 90° from the received clock signal. If the signal value of the second routing signal is the fourth signal value, the clock generated by the second clock generator has a phase difference of 270 with the received clock signal.
  • the input interface unit is provided with a multiplexer and a controller for providing a routing signal
  • the signal value of the routing signal can be controlled according to the packaging manner, thereby inputting the state of the multiplexer, thereby controlling the
  • the input state of the first input of the interface unit is input so that the input interface unit can be used when any of the TSV and MCM packages are employed.
  • the second input of the third multiplexer is clamped.
  • the signal input by the first input terminal of the input interface unit is output to the first input terminal of the third multiplexer through the third D flip-flop. And outputted by the third multiplexer to the first output of the input interface unit.
  • a signal input by the second input of the input interface unit is output to a second output of the input interface unit through a fifth D flip-flop.
  • the output interface unit and the corresponding input interface unit are packaged in a TSV manner.
  • the input interface unit receives data on a falling edge of the RX clock.
  • the first input of the third multiplexer is clamped.
  • the signal received by the second receiving end of the input interface unit is output to the second input of the third multiplexer via the fourth D flip-flop. And outputted by the third multiplexer to the first output of the input interface unit.
  • the signal received by the second receiving end of the input interface unit is simultaneously output to the second output of the input interface unit via the fifth D flip-flop.
  • the output interface unit and the corresponding input interface unit are packaged in an MCM manner.
  • the receiving end of the input interface unit processes the clock coming from the transmitting end with a DLL, producing a 90° and 270° phase clock. That is, the associated clock forms a phase difference of 90° and 270° with the received clock, and then the center signal is sampled by the data signal transmitted from the transmitting end under the phase clock.
  • the input interface unit provided by the present application does not need to change the circuit of the interface unit, and only by controlling the signal value of the routing signal, it is possible to select to use double rate (ie, MCM mode package) to transmit data, or The data is selected to be transmitted at a single rate (ie, TSV mode), that is, the input interface unit can be used when either of the TSV and the MCM is employed.
  • the input interface unit further includes a second clock generator.
  • the third D flip-flop, the fourth D flip-flop and the fifth D flip-flop have the same clock.
  • the input interface unit further includes a sixth D flip-flop, a seventh D flip-flop, and an eighth D flip-flop.
  • a sixth D flip-flop is coupled between the output of the third D flip-flop and the first input of the third multiplexer.
  • a seventh D flip-flop is coupled between the output of the fourth D flip-flop and the second input of the third multiplexer.
  • An eighth D flip-flop is connected to the output of the fifth D flip-flop.
  • the third D flip-flop, the fourth D flip-flop and the fifth D flip-flop are used to collect external information.
  • the sixth D flip-flop, the seventh D flip-flop and the eighth D flip-flop are used for sending external information collected by the third D flip-flop, the fourth D flip-flop and the fifth D flip-flop to the processing module inside the DIE .
  • the third D flip-flop has the same clock as the sixth D flip-flop
  • the fourth D flip-flop has the same clock as the seventh D flip-flop
  • the fifth D-flip-flop The clock of the eighth D flip-flop is the same. Synchronizing the third D flip-flop with the sixth D flip-flop, the fourth D flip-flop being synchronized with the seventh D flip-flop, the fifth D flip-flop and the eighth D flip-flop Synchronize.
  • the input end of the second clock generating port serves as a clock input end of the input interface unit.
  • the second input end of the third multiplexer is clamped by the first input end of the input interface unit
  • the input signal is output to the sixth D flip-flop through the third D flip-flop.
  • the sixth D flip-flop is output to the first input of the third multiplexer.
  • the third multiplexer is further output to the first output of the input interface unit.
  • a signal input by the second input terminal of the input interface unit is output to the eighth D flip-flop through the fifth D flip-flop.
  • the eighth D flip-flop is output to the second output of the input interface unit.
  • the second clock generator forms a 90° phase clock with the associated clock.
  • the input interface unit and the corresponding output interface unit are packaged in a TSV manner.
  • the input interface unit receives data on a falling edge of a receive side clock (RX clock).
  • the signal value of the second routing signal is a fourth signal value
  • the first input of the third multiplexer is clamped.
  • a signal received by the second receiving end of the input interface unit is output to the seventh D flip-flop via the fourth D flip-flop.
  • the seventh D flip-flop is output to the second input of the third multiplexer.
  • the third multiplexer is further output to the first output of the input interface unit.
  • the signal received by the second receiving end of the input interface unit is simultaneously outputted to the input end of the eighth D flip-flop via the fifth D flip-flop.
  • the eighth D flip-flop is output to the second output of the input interface unit.
  • the input interface unit and the corresponding output interface unit are encapsulated by the MCM method, and the receiving end of the input interface unit processes the clock that is sent by the transmitting end with a DLL to generate a 270° phase clock. Center the data for sampling.
  • the application further provides an input interface module, comprising at least one input interface unit according to the fourth aspect.
  • clocks of all input interface units in the input interface module are the same. All input interface units in the input interface module are synchronized.
  • all input interface units in the input interface module share a clock generator.
  • all input interface units in the input interface module are controlled by the same routing signal. All of the output interface units can be made to use the same package.
  • all input interface units in the input interface module share one controller. It is convenient to control the signal value the same, and reduce the number of controllers used.
  • the present application further provides a chip including a second internal processing unit and at least one input interface unit of the fourth aspect.
  • the second internal processing unit is used for DIE internal information processing.
  • the output of the input interface unit is connected to an input corresponding to the second internal processing unit.
  • the clocks of all the output interface units in the chip are the same. All of the output interface units in the chip are synchronized.
  • all of the output interface units in the chip are controlled by the same routing signal in order to enable all of the output interface units to adopt the same packaging.
  • the chip comprises a second internal processing unit and at least one input interface module of the fifth aspect.
  • the second internal processing unit is used for DIE internal information processing.
  • An output end of the input interface unit of the input interface module is connected to an input end corresponding to the second internal processing unit.
  • the clocks of all the output interface modules in the chip are the same. All of the output interface modules in the chip are synchronized.
  • all of the output interface modules in the chip are controlled by the same routing signal in order to enable all of the output interface modules to adopt the same packaging manner.
  • all of the output interface modules in the chip share a controller.
  • the present application further provides a chip, including the output interface unit of the first aspect and the input interface unit of the fourth aspect.
  • the first output of the output interface unit is coupled to the first input of the corresponding input interface unit.
  • the second output of the output interface unit is coupled to the second input of the corresponding input interface unit.
  • a clock phase difference between the output interface unit and the input interface unit is at least one of 0°, 90°, 180°, or 270°.
  • the output interface unit and the input interface unit are enabled to adopt a specific packaging manner.
  • the output interface unit is controlled by the first signal value
  • the input interface unit connected thereto is controlled by the third signal value.
  • a first output of the output interface unit is coupled to a first input of the input interface unit.
  • the second output end of the output interface unit is connected to the second input end of the corresponding input interface unit.
  • the clock output end of the output interface unit is connected to the clock input end of the corresponding input interface unit.
  • the output interface unit and the input interface unit are packaged in a TSV manner.
  • the output interface unit is controlled by a second signal value
  • the input interface unit connected thereto is controlled by a fourth signal value.
  • a second output of the output interface unit is coupled to a second input of the input interface unit.
  • the clock output of the output interface unit is coupled to the clock input of the input interface unit.
  • the chip comprises the output interface module of the third aspect and the input interface module of the sixth aspect.
  • the first output end of the output interface unit of the output interface module is connected to the first input end of the corresponding input interface unit of the input interface module.
  • the second output end of the output interface unit of the output interface module is connected to the second input end of the corresponding input interface unit of the input interface module.
  • 1a is a schematic longitudinal cross-sectional view showing a chip obtained by using a TSV package
  • Figure 1b shows the circuitry of the interface unit preset in the conventional TSV packaging method
  • FIG. 2 shows a circuit of an interface unit preset in a conventional MCM packaging method
  • FIG. 3 is a schematic structural diagram of an output interface unit according to an embodiment of the present invention.
  • FIG. 3b is a waveform diagram of an output interface unit in a TSV package mode according to an embodiment of the present invention.
  • 3c is a waveform diagram of an output interface unit in an MCM package mode according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of an output interface module according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a chip according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of an input interface unit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of an input interface module according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another chip according to the embodiment.
  • FIG. 9 is a schematic structural diagram of another chip according to the embodiment.
  • FIG. 10 is a schematic structural diagram of another chip according to the embodiment.
  • FIG. 3 is a schematic structural diagram of an output interface unit according to the embodiment, including a first D flip-flop 1, a second D flip-flop 2, a splitter 3, a first multiplexer 4, and a second multi-path selection.
  • the input D1 of the first D flip-flop 1 is the first input of the output interface unit.
  • the output terminal Q1 of the first D flip-flop 1 is connected to the input terminal I3 of the splitter 3.
  • the first output Z30 of the splitter 3 is the first output of the output interface unit.
  • the second output Z31 of the splitter 3 is connected to the first input I40 of the first multiplexer 4.
  • the input D2 of the second D flip-flop 2 is the second input of the output interface unit.
  • the output terminal Q2 of the second D flip-flop 2 is connected to the second input terminal I41 of the first multiplexer 4.
  • the output Z4 of the first multiplexer 4 is connected to the first input I51 of the second multiplexer 5.
  • the output Q2 of the second D flip-flop 2 is also connected to the second input I50 of the second multiplexer 5.
  • the output Z5 of the second multiplexer 5 is the second output of the output interface unit.
  • the output Z61 of the first clock generator 6 is the clock output of the output interface unit.
  • the output ports of the first controller 401 are connected to the routing signal input port S3 of the splitter 3 and the routing signal input port S5 of the second multiplexer 5, respectively. That is, the splitter 3 and the second multiplexer 5 are controlled by the same routing signal.
  • the D flip-flop may be a trigger that changes the output result according to the state of the clock signal under the action of a clock signal, or may implement the same or similar function of the D-type trigger. Circuit. Unless otherwise stated, the D flip-flops described in this application are rising edge flip-flops. The D flip-flop is used to register the received data and output the registered data to the output terminal under a specific clock.
  • the splitter may be a circuit that outputs a signal that should be output to different components according to different signal values of the routing signal.
  • the multiplexer may be a circuit that selects an output terminal as a signal output terminal according to a signal value of the routing signal, or a circuit that implements the same or similar function of the multiplexer.
  • the controller may be an input pin of the DIE or a circuit from within the DIE having the same function as the input pin.
  • the "connection” includes both two circuit devices being directly connected, and two circuit devices being connected by other circuit devices.
  • the “clamping” may mean that there is no signal output at the output of the circuit device, or it may mean that there is no signal input at the input of the circuit device.
  • the "clock same” may refer to an input that uses the same clock signal.
  • the output interface unit includes a splitter, a multiplexer and a controller, the output state of the first output end of the output interface unit can be changed by changing the signal value of the routing signal, so that the output interface unit is An output terminal and a second output terminal simultaneously perform signal output, or only the second output terminal of the output interface unit performs signal output.
  • the output interface unit can be used when adopting any one of TSV and MCM.
  • the first D flip-flop 1 has the same clock as the second D flip-flop 2.
  • the same clock means that the first D flip-flop 1 and the second D flip-flop 2 use the same clock signal input.
  • the first D flip-flop 1 and the second D flip-flop 2 are synchronized.
  • the first controller 401 is configured to provide a first routing signal, and the signal value of the first routing signal includes a first signal value or a second signal value.
  • the second output of the splitter and the first input of the second multiplexer are controlled by the same routing signal value. That is, if the splitter outputs a signal through the second output, the second multiplexer selects the signal input by the first input as an input signal. If the splitter outputs a signal through the first output, the second multiplexer selects a signal input by the second input as an input signal.
  • the first signal value is 0 and the second signal value is 1.
  • the first signal value is used to clamp the second output Z31 of the splitter 3 and the first input I51 of the second multiplexer 5.
  • the second signal value is used to clamp the first output Z30 of the splitter 3 and the second input I50 of the second multiplexer 5.
  • the second output terminal Z31 of the splitter 3 and the first input terminal I51 of the second multiplexer 5 are clamped.
  • the signal input by the first input terminal D1 of the output interface unit is output to the splitter 3 through the output terminal Q1 of the first D flip-flop 1, and then outputted to the output by the first output terminal Z30 of the splitter 3 The first output of the interface unit.
  • the signal input from the second input terminal of the output interface unit is output to the second multiplexer 5 via the output terminal Q2 of the second D flip-flop 2, and is output to the output by the output terminal Z5 of the second multiplexer 5 The second output of the interface unit.
  • the output interface unit and the corresponding input interface unit are encapsulated by a TSV method, the output interface unit transmits data on the rising edge of the TX clock, and the input interface unit receives data on the falling edge of the RX clock.
  • the RX clock is the associated clock of the TX clock.
  • the receiving end of the input interface unit uses the DLL to shape the associated clock, and uses the 180° phase clock generated by the DLL, and then performs data sampling on the center of the data signal sent by the transmitting end under the phase clock. Thereby reducing the dependence on the clock duty cycle and increasing the margin of data sampling.
  • the waveform is shown in Figure 3b.
  • the first output Z30 of the splitter 3 and the second input I51 of the second multiplexer 5 are clamped.
  • the signal input by the first input end of the output interface unit is output to the splitter 3 through the output terminal Q1 of the first D flip-flop 1, and then output to the first multi-channel by the second output terminal Z31 of the splitter 3.
  • the signal input by the second input terminal of the output interface unit is output to the second input terminal I41 of the first multiplexer 4 via the output terminal Q2 of the second D flip-flop 1.
  • the first multiplexer 4 selects a signal input using the first input terminal or the second input terminal as an input signal according to a clock signal generated by the first clock generator 6.
  • the first multiplexer 4 selects the signal of the first input as an input signal.
  • the first multiplexer 4 selects the signal of the second input as an input signal.
  • the signal is output to the first input terminal I51 of the second multiplexer 5 via the output terminal Z4 of the first multiplexer 4, and is output to the output interface unit by the output terminal Z5 of the second multiplexer 5 Second output.
  • the output interface unit and the corresponding input interface unit are encapsulated by the MCM method, and the transmitting end of the output interface unit shapes the input clock into a clock with an appropriate duty ratio through the DLL.
  • the data is transmitted using the 0°, 180° phase clock generated by the DLL, and the first phase transmits 1 bit of data.
  • the receiving end of the input interface unit corresponding to the output interface unit is processed by the DLL from the transmitting end to generate a 90° and 270° phase clock, and then the data signal sent by the transmitting end is centered under the phase clock. Center the data for sampling. Its waveform is shown in Figure 3c.
  • the input interface unit controls the signal value of the routing signal provided by the controller, it is possible to control the input interface unit to transmit data by double rate (ie, MCM mode encapsulation), or to transmit by using a single rate (ie, TSV mode package). data.
  • double rate ie, MCM mode encapsulation
  • TSV mode package ie, TSV mode package
  • the first signal value is 0 and the second signal value is 1.
  • the first signal value is used to clamp the first output Z30 of the splitter 3 and the second input I50 of the second multiplexer 5.
  • the second signal value is used to clamp the second output Z31 of the splitter 3 and the first input I51 of the second multiplexer 5.
  • FIG. 4 is a schematic structural diagram of an output interface module according to an embodiment of the present invention. As shown in FIG. 4, the output interface module includes at least two output interface units.
  • the first D flip-flop 101, the second D flip-flop 102, the splitter 103, the first multiplexer 104, the second multiplexer 105, the first controller 501, and the first clock generator 106 Forming a first output interface unit.
  • the first D flip-flop 201, the second D flip-flop 202, the splitter 203, the first multiplexer 204, the second multiplexer 205, the first controller 501, and the first clock generator 106 constitute a second Output interface unit.
  • clocks of all output interface units in the output interface module are the same. All of the output interface units are synchronized.
  • the two output interface units of the output interface module share a clock generator.
  • all of the output interface units in the output interface module can be controlled by the same routing signal.
  • all output interface units in the output interface module may share a controller, and the controller provides routing signals for the respective output interface units.
  • the signal value of the routing signal of one of the output interface units is 0, the signal value of the routing signals of the remaining output interface units is also 0.
  • the signal value of the routing signal of one of the output interface units is 1, the signal value of the routing signals of the remaining output interface units is also 1.
  • all of the output interface units of the output interface module may share the first clock generator 106 or may share the first controller 501.
  • the output interface unit is provided with a multiplexer and a controller for providing a routing signal
  • the signal value of the routing signal is controlled according to the packaging manner, thereby changing the first of all output interface units in the output interface module.
  • the output state of the output terminal enables the output interface module to be used regardless of whether the TSV mode package or the MCM mode package is used.
  • the embodiment further provides a chip, the chip includes a first internal processing unit and at least one output interface unit, wherein the first internal processing unit is used for DIE internal information processing, and the input end of the output interface unit and the first internal processing The output corresponding to the unit is connected.
  • the clocks of all of the output interface units in the chip are the same.
  • all of the output interface units in the chip can share a clock generator.
  • all of the output interface modules in the chip may share one controller.
  • FIG. 5 is a schematic structural diagram of a chip according to the embodiment.
  • the chip includes a first internal processing unit 600 and at least one output interface module 700.
  • the first internal processing unit 600 is used for DIE internal information.
  • the output interface module 700 includes at least two output interface units, and the input ends of all the output interface units are connected to the output ends corresponding to the first internal processing unit.
  • the clocks of all of the output interface units in the chip are the same.
  • all of the output interface units in the chip may share a clock generator 106.
  • all of the output interface modules in the chip may share one controller 501.
  • FIG. 6 is a schematic structural diagram of an input interface unit according to the embodiment.
  • the input interface unit includes a third D flip-flop 7, a fourth D flip-flop 8, a fifth D flip-flop 9, and a third The path selector 13, the sixth D flip-flop 10, the seventh D flip-flop 11, the eighth D flip-flop 12, the second clock generator 14, and the second controller 402.
  • the input D7 of the third D flip-flop 7 is the first input of the input interface unit.
  • the output terminal Q7 of the third D flip-flop 7 is connected to the input terminal D10 of the sixth D flip-flop 10.
  • the output terminal Q10 of the sixth D flip-flop 10 is connected to the first input terminal I130 of the third multiplexer 13.
  • the input D8 of the fourth D flip-flop 8 or the input D9 of the fifth D flip-flop 9 is the second input of the input interface unit.
  • the output terminal Q8 of the fourth D flip-flop 8 is connected to the input terminal D11 of the seventh D flip-flop 11.
  • the output terminal Q11 of the seventh D flip-flop 11 is connected to the second input terminal I131 of the third multiplexer 13.
  • the output Z13 of the third multiplexer 13 is the first output of the input interface unit.
  • the output terminal Q9 of the fifth D flip-flop 9 is connected to the input terminal D12 of the eighth D flip-flop 12.
  • the output terminal Q12 of the eighth D flip-flop 12 is the second output terminal of the input interface unit.
  • the input terminal I14 of the second clock generator 14 serves as the clock input terminal of the input interface unit.
  • the output Z141 of the second clock generator 14 serves as the clock output of the input interface unit.
  • the fourth flip-flop 8 is a falling edge flip-flop.
  • the third D flip-flop 7, the fourth D flip-flop 8 and the fifth D flip-flop 9 are used to collect external information.
  • the sixth D flip-flop 10, the seventh D flip-flop 11 and the eighth D flip-flop 12 are used to send the external information collected by the third D flip-flop 7, the fourth D flip-flop 8 and the fifth D flip-flop 9
  • the processing unit inside the DIE The sixth D flip-flop 10, the seventh D flip-flop 11 and the eighth D flip-flop 12 are used to send the external information collected by the third D flip-flop 7, the fourth D flip-flop 8 and the fifth D flip-flop 9
  • the processing unit inside the DIE The sixth D flip-flop 10, the seventh D flip-flop 11 and the eighth D flip-flop 12 are used to send the external information collected by the third D flip-flop 7, the fourth D flip-flop 8 and the fifth D flip-flop 9
  • the processing unit inside the DIE The processing unit inside the DIE.
  • the clocks of the third D flip-flop 7, the sixth D flip-flop 10, the fourth D flip-flop 8, the seventh D flip-flop 11, the fifth D flip-flop 9, and the eighth D flip-flop 12 are both the same.
  • the second controller 402 is configured to provide a second routing signal.
  • the signal value of the second routing signal includes a third signal value and a fourth signal value. Referring to FIG. 6, the third signal value is 0, and the fourth signal value is 1.
  • the third signal value is used to clamp the second input I131 of the third multiplexer 13, and to cause the second clock generator to form a 90[deg.] phase difference with the received clock.
  • the fourth signal value is used to clamp the first input I130 of the third multiplexer 13 and cause the second clock generator to form a 270 phase difference from the received clock.
  • the input interface unit includes a multiplexer and a controller, the input state of the first input end of the input interface unit can be changed by changing the signal value of the routing signal, so that the first input terminal of the input interface unit The signal input is performed simultaneously with the second input or only the second input is used for signal input.
  • the input interface unit can be used in any of the TSV and MCM packaging modes.
  • the second controller 402 provides the third signal value
  • the second input terminal I131 of the third multiplexer 13 is clamped, and the signal input by the first input terminal of the input interface unit passes through the third D
  • the output terminal Q7 of the flip-flop 7 is output to the sixth D flip-flop 10.
  • the output terminal Q10 of the sixth D flip-flop 10 is output to the first input terminal I130 of the third multiplexer 13.
  • the output Z13 of the third multiplexer 13 is then output to the first output of the input interface unit.
  • the signal input by the second input terminal of the input interface unit is output to the eighth D flip-flop 12 through the output terminal Q9 of the fifth D flip-flop 9.
  • the output terminal Q12 of the eighth D flip-flop 12 is output to the second output terminal of the input interface unit.
  • the second clock generator forms a 90° phase difference with the received clock (the associated clock).
  • the input interface unit and the corresponding output interface unit are encapsulated by a TSV method, and the input interface unit receives data on a falling edge of the RX clock.
  • the first input I130 of the third multiplexer 13 is clamped.
  • the signal received by the second receiving end of the input interface unit is output to the seventh D flip-flop 11 via the fourth D flip-flop 8.
  • the seventh D flip-flop 11 is output to the second input of the third multiplexer 13.
  • the third multiplexer 13 is then output to the first output of the input interface unit.
  • the signal received by the second receiving end of the input interface unit is simultaneously output to the input terminal of the eighth D flip-flop 12 via the fifth D flip-flop 9.
  • the eighth D flip-flop 12 is output to the second output of the input interface unit.
  • the input interface unit and the corresponding output interface unit are encapsulated by the MCM method, and the receiving end of the input interface unit processes the clock that is sent by the sending end with the DLL, so that the second clock generator and the second clock generator The associated clock forms a phase difference of 270°, and then the data signal sent by the transmitting end sent by the transmitting end is center-sampled under the phase clock.
  • FIG. 7 is a schematic structural diagram of an input interface module according to an embodiment of the present invention.
  • the input interface module includes at least two input interface units.
  • the input interface module includes a third D flip-flop 107, a fourth D flip-flop 108, a fifth D flip-flop 109, a sixth D flip-flop 110, a seventh D flip-flop 11, and an eighth D flip-flop 112.
  • the third multiplexer 113, the second controller 502, and the second clock generator 114 constitute a first input interface unit.
  • the second controller 502 and the second clock generator 114 constitute a second output interface unit.
  • clocks of all input interface units in the input interface module are the same.
  • all input interface units in the input interface module share a second clock generator 114.
  • all of the output interface units are controlled by the same routing signal in order to enable all input interface units in the input interface module to adopt the same packaging manner.
  • the embodiment further provides a chip including a second internal processing unit and at least one input interface unit.
  • the second internal processing unit is used for DIE internal information processing.
  • the output of the input interface unit is connected to an input corresponding to the second internal processing unit.
  • the clocks of all of the output interface units in the chip are the same. All of the output interface units are synchronized.
  • all the output interface units in the chip are controlled by the same routing signal in order to make all the output interface units be packaged in the same manner.
  • FIG. 8 is a schematic structural diagram of another chip according to the embodiment.
  • the chip includes a second internal processing unit 601 and at least one of the input interface modules 701.
  • the second internal processing unit is used for DIE internal information processing.
  • An output end of the input interface unit of the input interface module is connected to an input end corresponding to the second internal processing unit.
  • the clocks of all of the output interface modules in the chip are the same. All of the output interface modules are synchronized.
  • all of the output interface modules in the chip share a clock generator 114.
  • FIG. 9 is a schematic structural diagram of a chip according to the embodiment.
  • the compatible chip includes an output interface unit 800 and an input interface unit 801 disposed on a bare chip.
  • the first output end of the output interface unit in the output interface unit 900 is connected to the first input end of the corresponding input interface unit in the input interface unit 800.
  • the second output end of the output interface unit of the output interface unit is connected to the second input end of the corresponding input interface unit of the input interface unit.
  • a clock phase difference between the output interface unit and the input interface unit is at least one of 0°, 90°, 180°, or 270°.
  • the output interface unit and the input interface unit are enabled to adopt a specific package.
  • the output interface unit is controlled by the first signal value
  • the input interface unit connected thereto is controlled by the third signal value.
  • the first output end of the output interface unit is connected to the corresponding first input end of the input interface unit.
  • the second output end of the output interface unit is connected to the second input end of the corresponding input interface unit.
  • the clock output end of the output interface unit is connected to the clock input end of the input interface unit.
  • the output interface unit is controlled by the second signal value
  • the input interface unit connected thereto is controlled by the fourth signal value.
  • the second output end of the output interface unit is connected to the second input end of the corresponding input interface unit.
  • the clock output end of the output interface unit is connected to the clock input end of the corresponding input interface unit.
  • FIG. 10 is a schematic structural diagram of another chip according to the embodiment.
  • the chip includes the output interface module 700 and the input interface module 701.
  • the output interface module 700 includes at least two output interface units
  • the input interface module 701 includes at least two input interface units.
  • the first output end of the output interface unit of the output interface module is connected to the first input end of the corresponding input interface unit.
  • the second output end of the output interface unit of the output interface module is connected to the second input end of the corresponding input interface unit.
  • the clock phase difference between the output interface module 700 and the input interface module 701 is at least one of 0°, 90°, 180°, or 270°.
  • the output interface module 700 and the input interface module 701 can be configured in a specific package.
  • the output interface unit is controlled by the first signal value
  • the input interface unit connected thereto is controlled by the third signal value.
  • the first output of the output interface unit is in communication with the first input of the input interface unit.
  • the second output of the output interface unit is in communication with the second input of the input interface unit.
  • the clock output end of the output interface unit is in communication with the clock input end of the input interface unit.
  • the output interface unit and the input interface unit are TSV packages.
  • the output interface module 700 is controlled by the second signal value
  • the input interface module 701 connected thereto is controlled by the fourth signal value.
  • a second output of the output interface unit is coupled to a second input of the input interface unit.
  • the clock output end of the output interface unit is connected to the clock input end of the input interface unit.
  • the output interface unit and the input interface unit are encapsulated in an MCM manner.

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Abstract

一种输出接口单元和具有该接口单元的接口模块和芯片，以及一种相应的输入接口单元和具有该接口单元的接口模块和芯片。该输出接口单元包括第一D触发器、第二D触发器、分路器、第一多路选择器和第二多路选择器。该输入接口单元包括第三D触发器、第四D触发器、第五D触发器和第三多路选择器。上述输出接口单元和输入接口单元通过控制选路信号的信号值来控制分路器和多路选择器的输出状态和输入，从而实现使用同一个输出接口单元或者输入接口单元兼容TSV和MCM两种芯片封装方式。

Description

接口单元以及具有该接口单元的接口模块和芯片
本申请要求在2017年9月18日提交中国专利局、申请号为201710837865.7、发明名称为“接口单元以及具有该接口单元的接口模块和芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，尤其涉及一种接口单元以及具有该接口单元的接口模块和芯片。
背景技术
芯片的封装通常是将多个裸芯片(DIE)通过特定方法与其它部件整合为一块完整芯片，主要的封装方法有穿透硅通孔技术(through silicon via，TSV)和多芯片封装技术(multi chip package，MCP)两种。其中，TSV是指通过穿孔的方式实现芯片中不同层之间信号连接的封装方式，而MCM是指通过对die进行扩展叠加的方式实现芯片中不同层之间信号连接的封装方式。
采用TSV封装得到芯片的纵剖结构示意图如图1a所示，在该芯片中，die与封装基板(package substrate)900之间依次层压有微凸块层(microbumps)901、硅中介层(silicon interposer)902和覆晶反扣焊法凸块层(controlled collapsed chip connection bump,C4 bump)903,通过microbumps和silicon interposer实现DIE间信号的互连。
与TSV封装方式相比，采用MCM封装得到的芯片中没有microbumps和silicon interposer。DIE直接连到C4 bump，在package substrate内实现DIE间信号的互连。而在package substrate中走线需要的间距远大于在silicon interposer中走线的间距。
由此可见，由于两种封装方式所用的材料不同，两种封装方式加工工艺的精度也不同。因此，两种封装方式对裸芯片上的走线密度要求不同，TSV封装要求DIE的走线密度高，而MCM封装要求DIE的走线密度低。由于两种封装方式的走线密度不同，想要使采用两种封装方式获得的芯片在使用时具有相同的带宽，就要使它们管脚的数量和传输速率不同。所以在采用不同的封装方式时，要为DIE配置不同的能够形成特定走线密度的输出接口单元与对应的输入接口单元连接以实现DIE之间数据信号的互连。
例如，TSV封装方法中输出接口单元和对应的输入接口单元的电路如图1b所示，从图1b可以看出，采用TSV封装方式封装时，每个输出接口单元和对应的输入接口单元都需要两个数据信号传输端和一个时钟信号传输端。MCM封装方法中输出接口单元和对应的输入接口单元的电路如图2所示，从图2可以看出，采用MCM封装方法封装时，如果要实现与TSV封装方式具有相同的带宽，则每个输出接口单元和对应的输入接口单元仅需要一个数据信号传输端和一个时钟信号传输端。
由此可以看出，在相同带宽的要求下，对于不同的封装方式就要采用不同形式的输出接口单元和对应的输入接口单元，即，对于不同的封装方式就要采用不同形式的接口单元。
发明内容
本申请提供了一种接口单元以及具有该接口单元的接口模块和芯片，以解决TSV和MCM两种封装方法不能采用相同形式的接口单元的问题。
为了解决上述技术问题，本申请提供了如下几方面：
第一方面，本申请提供一种输出接口单元，包括第一D触发器，第二D触发器，分路器，第一多路选择器和第二多路选择器。所述分路器的输入端与所述第一D触发器的输出端连接。所述分路器的第二输出端与所述第一多路选择器的第一输入端连接。所述第二D触发器的输出端分别与所述第一多路选择器的第二输入端及所述第二多路选择器的第二输入端连接。所述第一多路选择器的输出端与所述第二多路选择器的第一输入端连接。所述分路器的第一输出端为所述输出接口单元的第一输出端。所述第二多路选择器的输出端为所述输出接口选择模块的第二输出端。所述分路器的第二输出端与所述第二多路选择器的第一输入端受相同选路信号的控制。
可选地，所述输出接口单元还包括第一控制器，所述第一控制器用于提供第一选路信号。所述第一选路信号的信号值包括第一信号值或者第二信号值。所述第一信号值用于对分路器的第二输出端和第二多路选择器的第一输入端钳位。所述第二信号值用于对分路器的第一输出端和第二多路选择器的第二输入端钳位。
如果第一选路信号的信号值为所述第一信号值，则分路器的第二输出端和第二多路选择器的第一输入端被钳位。所述分路器通过第二输出端输出信号。所述第二多路选择器选择由第一输入端输入的信号作为输入信号。
如果第一选路信号的信号值为所述第二信号值，则分路器的第一输出端和第二多路选择器的第二输入端被钳位。所述分路器通过第一输出端输出信号。所述第二多路选择器选择由第二输入端输入的信号作为输入信号。
可选地，所述输出接口单元还包括第一时钟发生器。所述第一多路选择器根据所述第一时钟发生器产生的时钟信号选择由第一输入端输入的信号作为输入信号或者选择由第二输入端输入的信号作为输入信号。
由于所述输出接口单元设置有分路器、多路选择器和用于提供选路信号的控制器，所以可以根据封装方式来控制选路信号的信号值，从而控制分路器的输出状态和多路选择器的输入状态，进而控制所述输出接口单元第一输出端的输出状态，使得在采用TSV和MCM中任意一种封装方式时都可以使用所述输出接口单元。
具体地，如果第一选路信号的信号值为所述第一信号值，分路器的第二输出端和第二多路选择器的第一输入端被钳位，其余电路未被钳位，这种情况下，所述输出接口单元与对应的输入接口单元可以采用TSV方式封装，输出接口单元在发送端时钟(TX时钟)上升沿发送数据，输入接口单元在接收端时钟(RX时钟)下降沿接收数据。RX时钟是TX时钟的随路时钟。在高频下，输入接口单元的接收端用数字锁相环(delay-locked loop，DLL)对随路时钟进行整形。利用DLL使随路时钟与接收到的时钟产生180°相位差。在此随路时钟下，对发送端发送的数据信号进行中心采样。从而减小对时钟占空比的依赖，增加数据采样的余量/裕度(timing margin)。其波形图如图3b所示。
如果第一选路信号的信号值为所述第二信号值，分路器的第一输出端和第二多路选择器的第二输入端被钳位，其余电路未被钳位，这种情况下，所述输出接口单元与对应的输入接口单元可以采用MCM方式封装，输出接口单元的发送端通过DLL将输入时钟整形为占 空比恰当的时钟。利用DLL产生的0°，180°相位时钟发送数据，每一个相位发送1bit数据。与之对应的输入接口单元的接收端将从发送端随路过来的时钟用DLL处理，产生90°和270°相位时钟。即，随路时钟与接收到的时钟形成90°和270°相位差，再在上述相位时钟下对发送端发送来的数据信号进行中心采样。其波形图如图3c所示。
由此可知，本申请提供的所述输出接口单元不需要改变接口单元的电路，仅通过控制选路信号的信号值，就能够实现选择用双倍速率(即，MCM方式封装)传输数据，或者选择用单倍速率(即，TSV方式封装)传输数据，即，实现在采用TSV和MCM中任意一种封装方式时都可以使用所述输出接口单元。
可选地，所述输出接口单元还包括第一时钟发生器。
在一种可能的实现方式中，所述第一D触发器与所述第二D触发器时钟相同。使得所述第一D触发器与所述第二D触发器同步。
在另一种可能实现的方式中，所述第一多路选择器根据第一时钟发生器产生的时钟信号选择采用第一输入端输入的信号或者第二输入端输入的信号作为输入信号。
在另一种可能实现的方式中，所述第一时钟发生器的输出端为所述输出接口单元的时钟输出端。
第二方面，本申请还提供一种输出接口模块，包括至少一个第一方面所述的输出接口单元。
在一种可能的实现方式中，所述输出接口模块中所有输出接口单元的时钟相同。使得所有所述输出接口单元同步。
进一步地，为减少时钟发生器的使用数量，所述输出接口模块中所有输出接口单元共用一个时钟发生器。
在另一种可能的实现方式中，所述输出接口模块中所有所述输出接口单元受相同选路信号的控制。使得所有所述输出接口单元能够采用相同的封装方式。
进一步地，为减少控制器的使用数量，所述输出接口模块中所有输出接口单元共用一个控制器。
第三方面，本申请还提供一种芯片，包括第一内部处理单元和至少一个第一方面所述的输出接口单元，其中，所述第一内部处理单元用于DIE内部信息处理，所述输出接口单元的输入端与第一内部处理单元对应的输出端连接。
在一种可能的实现方式中，所述芯片中所有所述输出接口单元的时钟相同。使得所述芯片中所有所述输出接口单元同步。
进一步地，为减少时钟发生器的使用数量，所述芯片中所有所述输出接口单元共用一个时钟发生器。
可选地，在所述芯片中所有所述输出接口单元受相同的选路信号控制。使得所有所述输出接口单元能够采用相同的封装方式。
进一步地，为减少控制器的使用数量，所述芯片中所有所述输出接口单元共用一个控制器。
或者，所述芯片包括第一内部处理单元和至少一个第二方面所述的输出接口模块。
所述输出接口模块中输出接口单元的输入端与第一内部处理单元对应的输出端连接。
在一种可能的实现方式中，所述芯片中所有所述输出接口模块的时钟相同。使得所有 所述输出接口模块同步。
进一步地，为减少时钟发生器的使用数量，所述芯片中所有所述输出接口模块共用一个时钟发生器。
在另一种可能的实现方式中，在所述芯片中所有所述输出接口模块受相同选路信号的控制。使得所有所述输出接口模块能够采用相同的封装方式。
进一步地，为减少控制器的使用数量，所述芯片中所有所述输出接口模块共用一个控制器。
第四方面，本申请还提供一种输入接口单元，包括第三D触发器、第四D触发器、第五D触发器和第三多路选择器。所述第三D触发器的输出端与所述第三多路选择器的第一输入端连接。所述第四D触发器的输出端与所述第三多路选择器的第二输入端连接。所述第三D触发器的输入端为所述输出接口单元的第一输入端。所述第四D触发器的输入端或者所述第五D触发器的输入端为所述输出接口单元的第二输入端。所述第三多路选择器的输出端为所述输出接口单元的第一输出端。所述第五D触发器的输出端为所述输出接口单元的第二输出端。所述第四触发器是下降沿触发器。
可选地，所述输入接口单元还包括第二控制器。所述第二控制器用于提供第二选路信号。所述第二选路信号的信号值包括第三信号值和第四信号值。所述第三信号值用于对第三多路器的第二输入端钳位。第四信号值用于对第三多路器的第一输入端钳位。
如果所述第二选路信号的信号值为所述第三信号值，所述第三多路选择器的第二输入端被钳位。所述第三多路选择器选择由第一输入端输入的信号作为输入信号。
如果所述第二选路信号的信号值为所述第四信号值，所述第三多路选择器的第一输入端被钳位。所述第三多路选择器选择由第二输入端输入的信号作为输入信号。
所述输入接口单元还包括第二时钟发生器。如果所述第二选路信号的信号值为所述第三信号值，所述第二时钟发生器产生的时钟与接收到的时钟信号具有90°相位差。如果所述第二选路信号的信号值为所述第四信号值，所述第二时钟发生器产生的时钟与接收到的时钟信号具有270°相位差。
由于所述输入接口单元设置有多路选择器和用于提供选路信号的控制器，所以可以根据封装方式来控制选路信号的信号值，从而多路选择器的输入状态，进而控制所述输入接口单元第一输入端的输入状态，使得在采用TSV和MCM中任意一种封装方式时都可以使用所述输入接口单元。
具体地，如果所述第二选路信号的信号值为第三信号值，第三多路选择器的第二输入端被钳位。由所述输入接口单元第一输入端输入的信号通过第三D触发器输出至第三多路选择器的第一输入端。再由第三多路选择器输出至所述输入接口单元的第一输出端。由所述输入接口单元第二输入端输入的信号通过第五D触发器输出至所述输入接口单元的第二输出端。这种情况下，所述输出接口单元与对应的输入接口单元采用TSV方式封装。所述输入接口单元在RX时钟下降沿接收数据。
如果所述第二选路信号的信号值为第四信号值，第三多路选择器的第一输入端被钳位。由所述输入接口单元的第二接收端接收到的信号经过第四D触发器输出至第三多路选择器的第二输入端。再由第三多路选择器输出至所述输入接口单元的第一输出端。由所述输入接口单元的第二接收端接收到的信号同时经过第五D触发器输出至所述输入接口单元的第 二输出端。这种情况下，所述输出接口单元与对应的输入接口单元采用MCM方式封装。输入接口单元的接收端将从发送端随路过来的时钟用DLL处理，产生90°和270°相位时钟。即，随路时钟与接收到的时钟形成90°和270°相位差，再在上述相位时钟下对发送端发送来的数据信号进行中心采样。
由此可知，本申请提供的所述输入接口单元不需要改变接口单元的电路，仅通过控制选路信号的信号值，就能够实现选择用双倍速率(即，MCM方式封装)传输数据，或者选择用单倍速率(即，TSV方式封装)传输数据，即，实现在采用TSV和MCM中任意一种封装方式时都可以使用所述输入接口单元。
在另一种可能的实现方式中，所述输入接口单元还包括第二时钟发生器。
可选地，所述第三D触发器、所述第四D触发器与所述第五D触发器的时钟相同。
在另一种可能的实现方式中，所述输入接口单元还包括第六D触发器、第七D触发器与第八D触发器。在所述第三D触发器的输出端与所述第三多路选择器的第一输入端之间连接有第六D触发器。在所述第四D触发器的输出端与所述第三多路选择器的第二输入端之间连接有第七D触发器。在所述第五D触发器的输出端连接有第八D触发器。所述第三D触发器、所述第四D触发器与所述第五D触发器用于采集外部信息。所述第六D触发器、第七D触发器与第八D触发器用于将第三D触发器、第四D触发器与第五D触发器采集到的外部信息送到DIE内部的处理模块。
可选地，所述第三D触发器与所述第六D触发器的时钟相同，所述第四D触发器与所述第七D触发器的时钟相同，所述第五D触发器与所述第八D触发器的时钟相同。使得所述第三D触发器与所述第六D触发器同步，所述第四D触发器与所述第七D触发器同步，所述第五D触发器与所述第八D触发器同步。
在另一种可能的实现方式中，所述第二时钟发生口器的输入端作为所述输入接口单元的时钟输入端。
在本实现方式中，如果所述第二选路信号的信号值为第三信号值，所述第三多路选择器的第二输入端被钳位，由所述输入接口单元第一输入端输入的信号通过所述第三D触发器输出至所述第六D触发器。再由所述第六D触发器输出至所述第三多路选择器的第一输入端。再由所述第三多路选择器输出至所述输入接口单元的第一输出端。由所述输入接口单元第二输入端输入的信号通过所述第五D触发器输出至所述第八D触发器。再由所述第八D触发器输出至所述输入接口单元的第二输出端。所述第二时钟发生器与随路时钟形成90°相位时钟。这种情况下，所述输入接口单元与对应的输出接口单元之间采用TSV方式封装。所述输入接口单元在接收端时钟(RX时钟)下降沿接收数据。
如果所述第二选路信号的信号值为第四信号值，所述第三多路选择器的第一输入端被钳位。由所述输入接口单元的第二接收端接收到的信号经过所述第四D触发器输出至第七D触发器。再由所述第七D触发器输出至所述第三多路选择器的第二输入端。再由所述第三多路选择器输出至所述输入接口单元的第一输出端。由所述输入接口单元的第二接收端接收到的信号同时经过所述第五D触发器输出至所述第八D触发器的输入端。再由所述第八D触发器输出至所述输入接口单元的第二输出端。这种情况下，所述输入接口单元与对应的输出接口单元之间通过MCM方式封装，所述输入接口单元的接收端将由发送端随路过来的时钟用DLL处理，产生270°相位时钟，再对数据进行中心采样。
第五方面，本申请还提供一种输入接口模块，包括至少一个第四方面所述的输入接口单元。
在一种可能的实现方式中，所述输入接口模块中所有输入接口单元的时钟相同。使得所述输入接口模块中所有输入接口单元同步。
进一步地，为减少时钟发生器的使用数量，所述输入接口模块中所有输入接口单元共用一个时钟发生器。
在另一种可能的实现方式中，所述输入接口模块中所有输入接口单元受相同选路信号的控制。使得所有所述输出接口单元能够采用相同的封装方式。
进一步地，所述输入接口模块中所有输入接口单元共用一个控制器。便于控制信号值相同，而且，减少控制器的使用数量。
第六方面，本申请还提供一种芯片，包括第二内部处理单元和至少一个第四方面所述输入接口单元。所述第二内部处理单元用于DIE内部信息处理。所述输入接口单元的输出端与第二内部处理单元对应的输入端连接。
在一种可能的实现方式中，所述芯片中所有所述输出接口单元的时钟相同。使得所述芯片中所有所述输出接口单元同步。
进一步地，为减少时钟发生器的使用数量，所述芯片中所有所述输出接口单元共用一个时钟发生器。
在另一种可能的实现方式中，为使得所有所述输出接口单元能够采用相同的封装方式，所述芯片中所有所述输出接口单元受相同的选路信号的控制。
进一步地，为减少控制器的使用数量，所述芯片中所有所述输出接口单元共用一个控制器。
或者，所述芯片包括第二内部处理单元和至少一个第五方面所述输入接口模块。所述第二内部处理单元用于DIE内部信息处理。所述输入接口模块中输入接口单元的输出端与第二内部处理单元对应的输入端连接。
在一种可能的实现方式中，所述芯片中所有所述输出接口模块的时钟相同。使得所述芯片中所有所述输出接口模块同步。
进一步地，为减少时钟发生器的使用数量，所述芯片中所有所述输出接口模块共用一个时钟发生器。
在另一种可能的实现方式中，为使得所有所述输出接口模块能够采用相同的封装方式，所述芯片中所有所述输出接口模块受相同的选路信号的控制。
可选地，为减少控制器的使用数量，所述芯片中所有所述输出接口模块共用一个控制器。
第七方面，本申请还提供一种芯片，包括第一方面所述输出接口单元和第四方面所述输入接口单元。所述输出接口单元的第一输出端与对应的输入接口单元的第一输入端连接。所述输出接口单元的第二输出端与对应的输入接口单元的第二输入端连接。
在一种可能的实现方式中，所述输出接口单元与所述输入接口单元的时钟相位差为0°、90°、180°或者270°中的至少一种。使得所述输出接口单元与所述输入接口单元能够采用特定的封装方式。
具体地，如果所述输出接口单元被第一信号值控制，则与之连接的所述输入接口单元 被第三信号值控制。所述输出接口单元的第一输出端与所述输入接口单元的第一输入端连接。所述输出接口单元的第二输出端与对应的所述输入接口单元的第二输入端连接。所述输出接口单元的时钟出端与对应的输入接口单元的时钟输入端连接。所述输出接口单元与所述输入接口单元采用TSV方式封装。
如果所述输出接口单元被第二信号值控制，则与之连接的所述输入接口单元被第四信号值控制。所述输出接口单元的第二输出端与所述输入接口单元的第二输入端连接。所述输出接口单元的时钟输出端与所述输入接口单元的时钟输入端连接。所述输出接口单元与所述输入接口单元采用MCM方式封装。
或者，所述芯片包括第三方面所述输出接口模块和第六方面所述输入接口模块。所述输出接口模块中输出接口单元的第一输出端与所述输入接口模块中对应的输入接口单元的第一输入端连接。所述输出接口模块中输出接口单元的第二输出端与所述输入接口模块中对应的输入接口单元的第二输入端连接。
附图说明
图1a示出采用TSV封装得到芯片的纵剖结构示意图；
图1b示出常规TSV封装方法中预设的接口单元的电路；
图2示出常规MCM封装方法中预设的接口单元的电路；
图3a为本实施例提供的一种输出接口单元的结构示意图；
图3b为本实施例提供的一种输出接口单元在TSV封装模式下的波形图；
图3c为本实施例提供的一种输出接口单元在MCM封装模式下的波形图；
图4为本实施例提供的一种输出接口模块的结构示意图；
图5为本实施例提供的一种芯片的结构示意图；
图6为本实施例提供的一种输入接口单元结构示意图；
图7为本实施例提供的一种输入接口模块结构示意图；
图8为本实施例提供的另一种芯片的结构示意图；
图9为本实施例提供的另一种芯片的结构示意图；
图10为本实施例提供的另一种芯片的结构示意图。
具体实施方式
图3a为本实施例提供的一种输出接口单元的结构示意图，包括第一D触发器1，第二D触发器2，分路器3，第一多路选择器4、第二多路选择器5、第一时钟发生器6和第一控制器401。第一D触发器1的输入端D1为所述输出接口单元的第一输入端。第一D触发器1的输出端Q1与分路器3的输入端I3连接。分路器3的第一输出端Z30为所述输出接口单元的第一输出端。分路器3的第二输出端Z31与第一多路选择器4的第一输入端I40连接。第二D触发器2的输入端D2为所述输出接口单元的第二输入端。第二D触发器2的输出端Q2与第一多路选择器4的第二输入端I41连接。第一多路选择器4的输出端Z4与第二多路选择器5的第一输入端I51连接。第二D触发器2的输出端Q2还与第二多路选择器5的第二输入端I50连接。第二多路选择器5的输出端Z5为所述输出接口单元的第二输出端。第一时钟发生器6的输出端Z61为所述输出接口单元的时钟输出端。第一控制器401的输出端口分别与分路器3的选路信号输入端口S3和第二多路选择器5的选路 信号输入端口S5连接。即，分路器3与第二多路选择器5受相同的选路信号控制。
在此需要说明的是，在本申请中，所述D触发器可以是在时钟信号作用下，输出结果根据时钟信号的状态而改变的触发器，也可以是实现D类触发器相同或相似功能的电路。除特殊说明，本申请中所述D触发器均为上升沿触发器。所述D触发器用于将接收到的数据寄存下来，在特定时钟下再将寄存的数据输出到输出端。所述分路器可以是根据选路信号的不同信号值将其所应输出的信号输出给不同元器件的电路。所述多路选择器可以是根据选路信号的信号值选择某一输出端作为信号输出端的电路，也可以是实现多路选择器相同或相似功能的电路。所述控制器可以是DIE的输入管脚，也可以是来自DIE内部的与输入管脚具有相同功能的电路。所述“连接”既包括两个电路器件直接相连，也包括两个电路器件通过其它电路器件相连。所述“钳位”可以是指使电路器件的输出端无信号输出，也可以是指使电路器件的输入端无信号输入。所述“时钟相同”可以是指采用同一时钟信号的输入。
由于所述输出接口单元包括分路器、多路选择器和控制器，通过改变选路信号的信号值就可以改变所述输出接口单元第一输出端的输出状态，使所述输出接口单元的第一输出端和第二输出端同时进行信号输出，或者仅使所述输出接口单元中的第二输出端进行信号输出。使得所述输出接口单元在采用TSV和MCM中任意一种封装方式时都可以使用。
在一种可能的实现方式中，第一D触发器1与第二D触发器2的时钟相同。所述时钟相同是指第一D触发器1与第二D触发器2采用同一时钟信号的输入。使得第一D触发器1、第二D触发器2同步。
第一控制器401用于提供第一选路信号，所述第一选路信号的信号值包括第一信号值或者第二信号值。所述分路器的第二输出端与所述第二多路选择器的第一输入端受相同的选路信号值控制。即，如果所述分路器通过第二输出端输出信号，则所述第二多路选择器选择第一输入端输入的信号作为输入信号。如果所述分路器通过第一输出端输出信号，则所述第二多路选择器选择第二输入端输入的信号作为输入信号。
在一种可能的实现方式中，结合图3a，第一信号值为0，第二信号值为1。第一信号值用于对分路器3的第二输出端Z31和第二多路选择器5的第一输入端I51钳位。第二信号值用于对分路器3的第一输出端Z30和第二多路选择器5的第二输入端I50钳位。
具体地，当第一控制器401提供第一信号值时，分路器3的第二输出端Z31和第二多路选择器5的第一输入端I51被钳位。由所述输出接口单元的第一输入端D1输入的信号经过第一D触发器1的输出端Q1输出至分路器3，再由分路器3的第一输出端Z30输出至所述输出接口单元的第一输出端。输出接口单元的第二输入端输入的信号经过第二D触发器2的输出端Q2输出至第二多路选择器5，再由第二多路选择器5的输出端Z5输出至所述输出接口单元的第二输出端。这种情况下，所述输出接口单元与对应的输入接口单元之间通过TSV方式封装，输出接口单元的TX时钟上升沿发送数据，输入接口单元在RX时钟下降沿接收数据。RX时钟是TX时钟的随路时钟。在高频下，输入接口单元的接收端用DLL对随路时钟进行整形，利用DLL产生的180°相位时钟，再在此相位时钟下对发送端发送来的数据信号进行中心进行数据采样。从而减小对时钟占空比的依赖，增加数据采样的余量。其波形图如图3b所示。
当控制器提供第二信号值时，分路器3的第一输出端Z30和第二多路选择器5的第二 输入端I51被钳位。由所述输出接口单元的第一输入端输入的信号经过第一D触发器1的输出端Q1输出至分路器3，再由分路器3的第二输出端Z31输出至第一多路选择器4的第一输入端I40。所述输出接口单元的第二输入端输入的信号经过第二D触发器1的输出端Q2输出至第一多路选择器4的第二输入端I41。第一多路选择器4根据第一时钟发生器6产生的时钟信号选择采用第一输入端或者第二输入端输入的信号作为输入信号。具体地，当第一时钟发生器6产生低电平时钟信号时，第一多路选择器4选择第一输入端的信号作为输入信号。当第一时钟发生器6产生高电平时钟信号时，第一多路选择器4选择第二输入端的信号作为输入信号。信号经过第一多路选择器4的输出端Z4输出至第二多路选择器5的第一输入端I51，再由第二多路选择器5的输出端Z5输出至所述输出接口单元的第二输出端。这种情况下，所述输出接口单元与对应的输入接口单元之间通过MCM方式封装，输出接口单元的发送端通过DLL将输入时钟整形为占空比恰当的时钟。利用DLL产生的0°，180°相位时钟发送数据，第一个相位发送1bit数据。与本输出接口单元对应的输入接口单元的接收端将从发送端随路过来的时钟用DLL处理，产生90°和270°相位时钟，再在此相位时钟下对发送端发送的数据信号进行中心对数据进行中心采样。其波形图如图3c所示。
从而，通过控制控制器提供的选路信号的信号值，能够实现控制所述输入接口单元采用双倍速率(即，MCM方式封装)传输数据，或者采用单倍速率(即，TSV方式封装)传输数据。
在另一种可能的实现方式中，第一信号值为0，第二信号值为1。第一信号值用于对分路器3的第一输出端Z30和第二多路选择器5的第二输入端I50钳位。第二信号值用于对分路器3的第二输出端Z31和第二多路选择器5的第一输入端I51钳位。具体内容请参见前述实现方式中的相关描述，在此不再赘述。
图4为本实施例提供的一种输出接口模块的结构示意图，如图4所示，所述输出接口模块包括至少两个所述输出接口单元。
具体地，第一D触发器101、第二D触发器102、分路器103、第一多路选择器104、第二多路选择器105、第一控制器501和第一时钟发生器106构成第一输出接口单元。第一D触发器201、第二D触发器202、分路器203、第一多路选择器204、第二多路选择器205、第一控制器501和第一时钟发生器106构成第二输出接口单元。
在一种可能的实现方式中，所述输出接口模块中所有输出接口单元的时钟相同。使得所有所述输出接口单元同步。
进一步地，为减少时钟发生器的使用数量以及便于控制时钟相同，所述输出接口模块中两个输出接口单元共用一个时钟发生器。
为使所述输出接口模块中所有输出接口单元能够采用相同的封装方式，所述输出接口模块中所有所述输出接口单元可以受相同选路信号的控制。
进一步地，为减少控制器的使用数量，所述输出接口模块中所有输出接口单元可以共用一个控制器，由该控制器来为各个输出接口单元提供选路信号。结合图4，在同一个输出接口模块中，当一个所述输出接口单元的选路信号的信号值为0时，其余所述输出接口单元的选路信号的信号值也为0。当一个所述输出接口单元的选路信号的信号值为1时，其余所述输出接口单元的选路信号的信号值也为1。进一步地，所述输出接口模块中的所 有输出接口单元可以共用第一时钟发生器106，也可以共用第一控制器501。
由于所述输出接口单元设置有多路选择器和用于提供选路信号的控制器，所以根据封装方式控制选路信号的信号值，从而改变所述输出接口模块中所有输出接口单元的第一输出端的输出状态，使得不论采用TSV方式封装还是采用MCM方式封装，均可使用所述输出接口模块。
本实施例还提供一种芯片，所述芯片包括第一内部处理单元和至少一个输出接口单元，其中，第一内部处理单元用于DIE内部信息处理，输出接口单元的输入端与第一内部处理单元对应的输出端连接。
为使得所述芯片中所有所述输出接口单元同步，所述芯片中所有所述输出接口单元的时钟相同。
进一步地，为便于控制时钟相同，而且，减少时钟发生器的使用数量，所述芯片中所有所述输出接口单元可以共用一个时钟发生器。
为使得所有所述输出接口单元的封装方式相同，所述芯片中所有所述输出接口单元受相同选路信号的控制。
进一步地，为便于控制信号值相同，而且，减少控制器的使用数量，所述芯片中所有所述输出接口模块可以共用一个控制器。
图5为本实施例提供的一种芯片的结构示意图，结合图5，所述芯片包括第一内部处理单元600和至少一个输出接口模块700，其中，第一内部处理单元600用于DIE内部信息处理，输出接口模块700包括至少两个输出接口单元，所有输出接口单元的输入端与第一内部处理单元对应的输出端连接。
为使得所述芯片中所有所述输出接口单元同步，所述芯片中所有所述输出接口单元的时钟相同。
进一步地，为便于控制时钟相同，而且，减少时钟发生器的使用数量，所述芯片中所有所述输出接口单元可以共用一个时钟发生器106。
为使得所有所述输出接口单元的封装方式相同，所述芯片中所有所述输出接口单元受相同选路信号的控制。
进一步地，为便于控制信号值相同，而且，减少控制器的使用数量，所述芯片中所有所述输出接口模块可以共用一个控制器501。
图6为本实施例提供的一种输入接口单元结构示意图，结合图6，所述输入接口单元包括第三D触发器7、第四D触发器8、第五D触发器9、第三多路选择器13、第六D触发器10、第七D触发器11、第八D触发器12、第二时钟发生器14和第二控制器402。第三D触发器7的输入端D7为所述输入接口单元的第一输入端。第三D触发器7的输出端Q7与第六D触发器10的输入端D10连接。第六D触发器10的输出端Q10与第三多路选择器13的第一输入端I130连接。第四D触发器8的输入端D8或者第五D触发器9的输入端D9为所述输入接口单元的第二输入端。第四D触发器8的输出端Q8与第七D触发器11的输入端D11连接。第七D触发器11的输出端Q11与第三多路选择器13的第二输入端I131连接。第三多路选择器13的输出端Z13为所述输入接口单元的第一输出端。第五D触发器9的输出端Q9与第八D触发器12的输入端D12连接。第八D触发器12的输出端Q12为所述输入接口单元的第二输出端。第二时钟发生器14的输入端I14作为所述输入接口 单元的时钟输入端。第二时钟发生器14的输出端Z141作为所述输入接口单元的时钟输出端。第四触发器8是下降沿触发器。
第三D触发器7、第四D触发器8与第五D触发器9用于采集外部信息。
第六D触发器10、第七D触发器11与第八D触发器12用于将第三D触发器7、第四D触发器8与第五D触发器9采集到的外部信息送到DIE内部的处理单元。
在本实现方式中，第三D触发器7、第六D触发器10、第四D触发器8、第七D触发器11、第五D触发器9与第八D触发器12的时钟均相同。
第二控制器402用于提供第二选路信号。所述第二选路信号的信号值包括第三信号值和第四信号值。结合图6，所述第三信号值为0，所述第四信号值为1。第三信号值用于对第三多路选择器13的第二输入端I131钳位，并使第二时钟发生器与接收到的时钟形成90°相位差。第四信号值用于对第三多路选择器13的第一输入端I130钳位，并使第二时钟发生器与接收到的时钟形成270°相位差。
由于所述输入接口单元包括多路选择器和控制器，通过改变选路信号的信号值就可以改变所述输入接口单元第一输入端的输入状态，使所述输入接口单元中的第一输入端和第二输入端同时进行信号输入或者仅使第二输入端进行信号输入。使得所述输入接口单元在TSV和MCM中任意一种封装方式时都可以使用所述输入接口单元。
具体地，当第二控制器402提供第三信号值时，第三多路选择器13的第二输入端I131被钳位，由所述输入接口单元第一输入端输入的信号通过第三D触发器7的输出端Q7输出至第六D触发器10。再由第六D触发器10的输出端Q10输出至第三多路选择器13的第一输入端I130。再由第三多路选择器13的输出端Z13输出至所述输入接口单元的第一输出端。由所述输入接口单元第二输入端输入的信号通过第五D触发器9的输出端Q9输出至第八D触发器12。再由第八D触发器12的输出端Q12输出至所述输入接口单元的第二输出端。第二时钟发生器与接收到的时钟(随路时钟)形成90°相位差。这种情况下，所述输入接口单元与对应的输出接口单元之间通过TSV方式封装，所述输入接口单元在RX时钟下降沿接收数据。
当第二控制器402提供第四信号值时，第三多路选择器13的第一输入端I130被钳位。由所述输入接口单元的第二接收端接收到的信号经过第四D触发器8输出至第七D触发器11。再由第七D触发器11输出至第三多路选择器13的第二输入端。再由第三多路选择器13输出至所述输入接口单元的第一输出端。由所述输入接口单元的第二接收端接收到的信号同时经过第五D触发器9输出至第八D触发器12的输入端。再由第八D触发器12输出至所述输入接口单元的第二输出端。这种情况下，所述输入接口单元与对应的输出接口单元之间通过MCM方式封装，所述输入接口单元的接收端将由发送端随路过来的时钟用DLL处理，使得第二时钟发生器与随路时钟形成270°相位差，再在上述相位时钟下对发送端发送来的发送端发送来的进行数据信号进行中心采样。
图7为本实施例提供的一种输入接口模块结构示意图，结合图7，所述输入接口模块包括至少两个所述输入接口单元。
具体地，所述输入接口模块包括第三D触发器107、第四D触发器108、第五D触发器109、第六D触发器110、第七D触发器11、第八D触发器112、第三多路选择器113、第二控制器502和第二时钟发生器114构成第一输入接口单元。第三D触发器207、第四 D触发器208、第五D触发器209、第六D触发器210、第七D触发器211、第八D触发器212、第三多路选择器213、第二控制器502和第二时钟发生器114构成第二输出接口单元。
在一种可实现的方式中，所述输入接口模块中所有输入接口单元的时钟相同。
在另一种可实现的方式中，为便于控制时钟相同，而且，减少时钟发生器的使用数量，所述输入接口模块中所有输入接口单元共用第二时钟发生器114。
在另一种可实现的方式中，为使所述输入接口模块中所有输入接口单元能够采用相同的封装方式，所有所述输出接口单元受相同选路信号的控制。
进一步地，为减少控制器的使用数量所述输入接口模块中所有输入接口单元共用第二控制器502。
本实施例还提供一种芯片，所述芯片包括第二内部处理单元和至少一个输入接口单元。所述第二内部处理单元用于DIE内部信息处理。所述输入接口单元的输出端与第二内部处理单元对应的输入端连接。
在一种可实现的方式中，所述芯片中所有所述输出接口单元的时钟相同。使得所有所述输出接口单元同步。
进一步地，为便于控制时钟相同，而且，减少时钟发生器的使用数量，所述芯片中所有所述输出接口单元共用一个时钟发生器。
在另一种可能的实现方式中，为使所有所述输出接口单元的封装方式相同，所述芯片中所有所述输出接口单元受到相同选路信号的控制。
进一步地，为便于控制信号值相同，而且，减少控制器的使用数量，所述芯片中所有所述输出接口单元共用一个控制器。
图8为本实施例提供的另一种芯片的结构示意图，结合图8，所述芯片包括第二内部处理单元601和至少一个所述输入接口模块701。所述第二内部处理单元用于DIE内部信息处理。所述输入接口模块中输入接口单元的输出端与第二内部处理单元对应的输入端连接。
在一种可实现的方式中，所述芯片中所有所述输出接口模块的时钟相同。使得所有所述输出接口模块同步。
进一步地，为便于控制时钟相同，而且，减少时钟发生器的使用数量，所述芯片中所有所述输出接口模块共用一个时钟发生器114。
在另一种可能的实现方式中，为使所有所述输出接口单元的封装方式相同，所述芯片中所有所述输出接口模块受到相同选路信号的控制。
进一步地，为便于控制信号值相同，而且，减少控制器的使用数量，所述芯片中所有所述输出接口模块共用第二控制器502。
图9为本实施例提供的一种芯片的结构示意图，结合图9，所述兼容式芯片包括设置于裸芯片上的输出接口单元800和输入接口单元801。所述输出接口单元900中输出接口单元的第一输出端与所述输入接口单元800中对应的输入接口单元的第一输入端连接。所述输出接口单元中输出接口单元的第二输出端与所述输入接口单元中对应的输入接口单元的第二输入端连接。
在一种可能的实现方式中，所述输出接口单元与所述输入接口单元的时钟相位差为0°、90°、180°或者270°中的至少一种。使得所述输出接口单元与所述输入接口单元能 够采用特定的封装方式。
在另一种可能的实现方式中，如果所述输出接口单元被第一信号值控制，则与之连接的所述输入接口单元被第三信号值控制。所述输出接口单元的第一输出端与对应的所述输入接口单元的第一输入端连接。所述输出接口单元的第二输出端与对应的所述输入接口单元的第二输入端连接。所述输出接口单元的时钟出端与所述输入接口单元的时钟输入端连接。所述输出接口单元与所述输入接口单元采用TSV方式封装。
在另一种可能的实现方式中，如果所述输出接口单元被第二信号值控制，则与之连接的所述输入接口单元被第四信号值控制。所述输出接口单元的第二输出端与对应的所述输入接口单元的第二输入端连接。所述输出接口单元的时钟出端与对应的所述输入接口单元的时钟输入端连接。所述输出接口单元与对应的所述输入接口单元采用MCM方式封装。
图10为本实施例提供的另一种芯片的结构示意图，结合图10，所述芯片包括所述输出接口模块700和所述输入接口模块701。所述输出接口模块700包括至少两个输出接口单元，所述输入接口模块701包括至少两个输入接口单元。其中，所述输出接口模块中输出接口单元的第一输出端与对应的输入接口单元的第一输入端连接。所述输出接口模块中输出接口单元的第二输出端与对应的输入接口单元的第二输入端连接。
在一种可能的实现方式中，所述输出接口模块700与所述输入接口模块701的时钟相位差为0°、90°、180°或者270°中的至少一种。使得所述输出接口模块700与所述输入接口模块701可以采用特定的封装方式。
在另一种可能的实现方式中，如果所述输出接口单元被第一信号值控制，则与之连接的所述输入接口单元被第三信号值控制。所述输出接口单元的第一输出端与所述输入接口单元的第一输入端连通。所述输出接口单元的第二输出端与所述输入接口单元的第二输入端连通。所述输出接口单元的时钟出端与所述输入接口单元的时钟输入端连通。此种情况下，所述输出接口单元与所述输入接口单元为TSV封装。
在另一种可能的实现方式中，如果所述输出接口模块700被第二信号值控制，则与之连接的所述输入接口模块701被第四信号值控制。所述输出接口单元的第二输出端与所述输入接口单元的第二输入端连接。所述输出接口单元的时钟出端与所述输入接口单元的时钟输入端连接。此种情况下，所述输出接口单元与所述输入接口单元采用MCM方式封装。
以上结合具体实施方式和范例性实例对本申请进行了详细说明，不过这些说明并不能理解为对本申请的限制。本领域技术人员理解，在不偏离本申请精神和范围的情况下，可以对本申请技术方案及其实施方式进行多种等价替换、修饰或改进，这些均落入本申请的范围内。本申请的保护范围以所附权利要求为准。

Claims (14)

  1. 一种输出接口单元，其特征在于，包括第一D触发器，第二D触发器，分路器，第一多路选择器和第二多路选择器，其中，
    所述分路器的输入端与所述第一D触发器的输出端连接，所述分路器的第二输出端与所述第一多路选择器的第一输入端连接；
    所述第二D触发器的输出端分别与所述第一多路选择器的第二输入端及所述第二多路选择器的第二输入端连接；
    所述第一多路选择器的输出端与所述第二多路选择器的第一输入端连接；
    所述分路器的第一输出端为所述输出接口单元的第一输出端，所述第二多路选择器的输出端为所述输出接口选择模块的第二输出端；
    所述分路器的第二输出端与所述第二多路选择器的第一输入端受相同选路信号的控制。
  2. 根据权利要求1所述输出接口单元，其特征在于，所述输出接口单元还包括第一控制器，所述第一控制器用于提供第一选路信号，所述第一选路信号的信号值包括第一信号值和第二信号值，其中，
    如果所述第一选路信号的信号值为所述第一信号值，则分路器的第二输出端和第二多路选择器的第一输入端被钳位，所述分路器通过第二输出端输出信号，所述第二多路选择器选择由第一输入端输入的信号作为输入信号；
    如果所述第一选路信号的信号值为所述第二信号值，则分路器的第一输出端和第二多路选择器的第二输入端被钳位，所述分路器通过第一输出端输出信号，所述第二多路选择器选择由第二输入端输入的信号作为输入信号。
  3. 根据权利要求1或2所述输出接口单元，其特征在于，所述输出接口单元还包括第一时钟发生器，所述第一时钟发生器用于产生时钟信号，所述第一多路选择器根据所述时钟信号选择由第一输入端输入的信号或者由第二输入端输入的信号作为输入信号。
  4. 一种芯片，其特征在于，包括第一内部处理单元和至少一个如权利要求1至3任一顶所述输出接口单元，其中，所述第一内部处理单元用于DIE内部信息处理，所述输出接口单元的输入端与所述第一内部处理单元对应的输出端连接。
  5. 根据权利要求4所述的芯片，其特征在于，所述芯片中所有所述输出接口单元的时钟相同，所有所述输出接口单元受到相同选路信号的控制。
  6. 一种输入接口单元，其特征在于，包括第三D触发器、第四D触发器、第五D触发器和第三多路选择器，其中，
    所述第三多路选择器的第一输入端与所述第三D触发器的输出端连接，
    所述第三多路选择器的第二输入端与所述第四D触发器的输出端连接，
    所述第三多路选择器的输出端为所述输出接口单元的第一输出端；
    所述第三D触发器的输入端为所述输出接口单元的第一输入端，所述第四D触发器的输入端或者所述第五D触发器的输入端为所述输出接口单元的第二输入端；
    所述第五D触发器的输出端为所述输出接口单元的第二输出端；
    所述第四D触发器是下降沿触发器。
  7. 根据权利要求6所述输入接口单元，其特征在于，所述输入接口单元还包括第二控制器，所述第二控制器用于提供第二选路信号，所述第二选路信号的信号值包括第三信号值和第四信号值，其中，
    如果第二选路信号的信号值为所述第三信号值，所述第三多路选择器的第二输入端被钳位，所述第三多路选择器选择由第一输入端输入的信号作为输入信号；
    如果第二选路信号的信号值为所述第四信号值，所述第三多路选择器的第一输入端被钳位，所述第三多路选择器选择由第二输入端输入的信号作为输入信号。
  8. 根据权利要求6或7所述输入接口单元，其特征在于，所述输入接口单元还包括第二时钟发生器，
    如果第二选路信号的信号值为所述第三信号值时，所述第二时钟发生器产生的时钟与接收到的时钟信号具有90°相位差；
    如果第二选路信号的信号值为所述第四信号值时，所述第二时钟发生器产生的时钟与接收到的时钟信号具有270°相位差。
  9. 根据权利要求6至8任一项所述输入接口单元，其特征在于，所述输入接口单元还包括第六D触发器、第七D触发器与第八D触发器，其中，
    所述第六D触发器的输入端与所述第三D触发器的输出端连接，所述第六D触发器的输出端与所述第三多路选择器的第一输入端连接；
    所述第七D触发器的输入端与所述第四D触发器的输出端连接，所述第七D触发器的输出端与所述第三多路选择器的第二输入端连接；
    所述第八D触发器的输入端与所述第五D触发器的输出端连接，所述第八D触发器的输出端为所述输出接口单元的第二输出端。
  10. 根据权利要求6至9任一项所述输入接口单元，其特征在于，所述第三D触发器与所述第六D触发器的时钟相同，所述第四D触发器与第七D触发器的时钟相同，所述第五D触发器与第八D触发器的时钟相同。
  11. 一种芯片，其特征在于，包括第二内部处理单元和至少一个如权利要求6至10任一项所述输入接口单元，其中，所述第二内部处理单元用于DIE内部信息处理，所述输入接口单元的输出端与所述第二内部处理单元对应的输入端连接。
  12. 根据权利要求11所述的芯片，其特征在于，所述芯片中所有所述输入接口单元的时钟相同，所有所述输入接口单元受相同选路信号的控制。
  13. 一种芯片，其特征在于，包括权利要求1至3任一项所述输出接口单元和权利要求6至10任一项所述输入接口单元，其中，
    所述输出接口单元的第一输出端与对应的输入接口单元的第一输入端连接；
    所述输出接口单元的第二输出端与对应的输入接口单元的第二输入端连接。
  14. 根据权利要求13所述兼容式芯片，其特征在于，所述输出接口单元与对应的输入接口单元的时钟相位差为0°、90°、180°或者270°中的至少一种。
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