JP2010165777A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP2010165777A
JP2010165777A JP2009005618A JP2009005618A JP2010165777A JP 2010165777 A JP2010165777 A JP 2010165777A JP 2009005618 A JP2009005618 A JP 2009005618A JP 2009005618 A JP2009005618 A JP 2009005618A JP 2010165777 A JP2010165777 A JP 2010165777A
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JP
Japan
Prior art keywords
bus bar
die pad
semiconductor device
sealing body
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009005618A
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English (en)
Japanese (ja)
Other versions
JP2010165777A5 (https=
Inventor
Noriyuki Takahashi
典之 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2009005618A priority Critical patent/JP2010165777A/ja
Publication of JP2010165777A publication Critical patent/JP2010165777A/ja
Publication of JP2010165777A5 publication Critical patent/JP2010165777A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07521—Aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

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  • Lead Frames For Integrated Circuits (AREA)
JP2009005618A 2009-01-14 2009-01-14 半導体装置及びその製造方法 Pending JP2010165777A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009005618A JP2010165777A (ja) 2009-01-14 2009-01-14 半導体装置及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009005618A JP2010165777A (ja) 2009-01-14 2009-01-14 半導体装置及びその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012208061A Division JP5420737B2 (ja) 2012-09-21 2012-09-21 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2010165777A true JP2010165777A (ja) 2010-07-29
JP2010165777A5 JP2010165777A5 (https=) 2012-02-16

Family

ID=42581747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009005618A Pending JP2010165777A (ja) 2009-01-14 2009-01-14 半導体装置及びその製造方法

Country Status (1)

Country Link
JP (1) JP2010165777A (https=)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013128019A (ja) * 2011-12-16 2013-06-27 Renesas Electronics Corp 半導体装置
JP2013197426A (ja) * 2012-03-22 2013-09-30 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
JP2014220439A (ja) * 2013-05-10 2014-11-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US9812388B2 (en) 2016-01-27 2017-11-07 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
CN113838827A (zh) * 2020-06-24 2021-12-24 上海凯虹科技电子有限公司 引线框架及封装体
WO2024198071A1 (zh) * 2023-03-30 2024-10-03 宁波德洲精密电子有限公司 一种lqfp引线框架结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091489A (ja) * 1998-09-15 2000-03-31 Anam Semiconductor Inc 半導体パッケ―ジ用リ―ドフレ―ム及び、これを用いた半導体パッケ―ジ
JP2002076234A (ja) * 2000-08-23 2002-03-15 Rohm Co Ltd 樹脂封止型半導体装置
JP2007324402A (ja) * 2006-06-01 2007-12-13 Shinko Electric Ind Co Ltd リードフレームとその製造方法及び半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091489A (ja) * 1998-09-15 2000-03-31 Anam Semiconductor Inc 半導体パッケ―ジ用リ―ドフレ―ム及び、これを用いた半導体パッケ―ジ
JP2002076234A (ja) * 2000-08-23 2002-03-15 Rohm Co Ltd 樹脂封止型半導体装置
JP2007324402A (ja) * 2006-06-01 2007-12-13 Shinko Electric Ind Co Ltd リードフレームとその製造方法及び半導体装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013128019A (ja) * 2011-12-16 2013-06-27 Renesas Electronics Corp 半導体装置
JP2013197426A (ja) * 2012-03-22 2013-09-30 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
JP2014220439A (ja) * 2013-05-10 2014-11-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US9812388B2 (en) 2016-01-27 2017-11-07 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
US10090237B2 (en) 2016-01-27 2018-10-02 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
CN113838827A (zh) * 2020-06-24 2021-12-24 上海凯虹科技电子有限公司 引线框架及封装体
WO2024198071A1 (zh) * 2023-03-30 2024-10-03 宁波德洲精密电子有限公司 一种lqfp引线框架结构

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