JP2010045302A - 半導体装置の製造方法、及び半導体装置 - Google Patents
半導体装置の製造方法、及び半導体装置 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
【解決手段】下地層上に、線幅が一定の線状部を有する第1のパターン14aと、第1のパターンの線状部に近接した部分と線状部から離れた部分を有し、第1のパターンとは独立して、又は第1のパターンに接続されて閉ループ形状を構成する第2のパターン14bとを形成する。第2のパターンの第1のパターンの線状部から離れた部分141aで閉ループカットを行う。
【選択図】図2
Description
図1(a)〜(h)は、本発明の第1の実施の形態に係る半導体装置の製造工程を示す断面図、図2(a)〜(c)は、図1(d)に示す工程と図1(e)に示す工程との間に行われる閉ループカット工程を示す平面図である。
図3(a)〜(h)は、本発明の第2の実施の形態に係る半導体装置の製造工程を示す断面図、図4(a)〜(c)は、図3(h)の工程の後に行われる閉ループカット工程を示す平面図である。第1の実施の形態では、予め配線材料を形成しておき、側壁パターンの端部を閉ループカットした後に配線材料から配線パターンを形成したが、本実施の形態は、閉ループ形状の配線パターンを形成した後に配線パターンの端部を閉ループカットするものである。
Claims (5)
- 下地層上に、線幅が一定の線状部を有する第1のパターンと、前記第1のパターンの前記線状部に近接した部分と前記線状部から離れた部分を有し、前記第1のパターンとは独立して、又は前記第1のパターンに接続されて閉ループ形状を構成する第2のパターンとを形成する第1の工程と、
前記第2のパターンの前記第1のパターンの前記線状部から離れた部分で閉ループカットを行う第2の工程とを含む半導体装置の製造方法。 - 下地層上に、線幅が一定の線状部を有する第1のパターンと、前記第1のパターンの前記線状部との間に第1の間隔を有する、前記第1のパターンに平行な部分を備え、前記第1のパターンとは独立して、又は前記第1のパターンに接続されて閉ループ形状を構成する第2のパターンとを形成する第1の工程と、
前記第1のパターンの前記線状部との間に前記第1の間隔よりも大きい第2の間隔を有してレジストを前記第2のパターンの一部に形成し、前記レジストが形成された前記第2のパターンの部分で閉ループカットを行う第2の工程とを含む半導体装置の製造方法。 - 下地層上に、芯材パターンを形成し、前記芯材パターンの側面に側壁パターンを形成した後、前記芯材パターンを除去することにより、線幅が一定の線状部を有する閉ループ形状の第1のパターンと、前記第1のパターンの前記線状部に近接した部分と前記線状部から離れた部分とを有し、前記第1のパターンとは独立して、又は前記第1のパターンに接続されて閉ループ形状を構成する第2のパターンとを形成する第1の工程と、
前記第2のパターンの前記第1のパターンの前記線状部から離れた部分で閉ループカットを行う第2の工程とを含む半導体装置の製造方法。 - 下地層上に、所定の周期で配列された複数の第1のパターンからなる第1のパターン群と、前記所定の周期で配列された複数の第2のパターンからなり、前記複数の第2のパターンのうち、少なくとも前記第1の配線パターン群に最も近接する第2のパターンは、前記第1のパターン群に平行な平行部と、前記第2のパターン群から離れた部分とを有し、前記第1のパターン群とは独立して、又は前記第1のパターン群に接続されて閉ループ形状を構成する第2のパターン群とを形成する第1の工程と、
前記第2のパターンの前記第1のパターン群から離れた部分で閉ループカットを行う第2の工程とを含む半導体装置の製造方法。 - 所定の周期で配列された複数の第1の配線パターンからなる第1の配線パターン群と、
前記所定の周期で配列された複数の第2の配線パターンからなる第2の配線パターン群とを備え、
前記複数の第2の配線パターンのうち、少なくとも前記第1の配線パターン群に最も近接する第2の配線パターンは、前記第1の配線パターン群に平行な平行部と、前記平行部に接続して前記第1の配線パターン群から遠ざかるように設けられ、かつ前記第1の配線パターン群に平行でない非平行部とを有する半導体装置。
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JP2008209849A JP4789158B2 (ja) | 2008-08-18 | 2008-08-18 | 半導体装置の製造方法、及び半導体装置 |
US12/542,540 US8183148B2 (en) | 2008-08-18 | 2009-08-17 | Method of fabricating semiconductor device and semiconductor device |
US14/284,709 USRE46100E1 (en) | 2008-08-18 | 2014-05-22 | Method of fabricating semiconductor device and semiconductor device |
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Cited By (4)
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KR20120017547A (ko) * | 2010-08-19 | 2012-02-29 | 삼성전자주식회사 | 라인 패턴 구조물의 형성 방법 |
KR20130094169A (ko) * | 2012-02-15 | 2013-08-23 | 삼성전자주식회사 | 도전 라인의 전기적 접촉 신뢰성을 증가시키기 위해서 수정 직사각형 마스크 패턴을 이용하는 집적회로 장치 제조 방법 |
US9653314B2 (en) | 2014-09-09 | 2017-05-16 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
KR101876941B1 (ko) * | 2011-12-22 | 2018-07-12 | 에스케이하이닉스 주식회사 | 반도체 소자의 제조 방법 |
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JP5395837B2 (ja) | 2011-03-24 | 2014-01-22 | 株式会社東芝 | 半導体装置の製造方法 |
JP2013197266A (ja) | 2012-03-19 | 2013-09-30 | Toshiba Corp | 半導体装置およびその製造方法 |
US8637982B2 (en) | 2012-04-18 | 2014-01-28 | Sandisk Technologies Inc. | Split loop cut pattern for spacer process |
KR102059183B1 (ko) | 2013-03-07 | 2019-12-24 | 삼성전자주식회사 | 반도체 장치의 제조 방법 및 이에 의해 제조된 반도체 장치 |
US9911693B2 (en) | 2015-08-28 | 2018-03-06 | Micron Technology, Inc. | Semiconductor devices including conductive lines and methods of forming the semiconductor devices |
US10483202B2 (en) * | 2016-02-22 | 2019-11-19 | Toshiba Memory Corporation | Semiconductor device having a wiring line with an end portion having rounded side surfaces and manufacturing method thereof |
US9847339B2 (en) * | 2016-04-12 | 2017-12-19 | Macronix International Co., Ltd. | Self-aligned multiple patterning semiconductor device fabrication |
CN108550522B (zh) * | 2018-04-27 | 2020-09-04 | 上海集成电路研发中心有限公司 | 一种多次图形化的方法 |
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USRE46100E1 (en) | 2016-08-09 |
US8183148B2 (en) | 2012-05-22 |
US20100038795A1 (en) | 2010-02-18 |
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