JP2010045162A - 半導体装置、半導体装置の製造方法、及びカメラモジュール - Google Patents
半導体装置、半導体装置の製造方法、及びカメラモジュール Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 117
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 239000000945 filler Substances 0.000 claims abstract description 48
- 230000001681 protective effect Effects 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 7
- 230000000149 penetrating effect Effects 0.000 abstract description 2
- 230000002411 adverse Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 127
- 238000000034 method Methods 0.000 description 15
- 239000011241 protective layer Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000009719 polyimide resin Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000008602 contraction Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- -1 polytetrafluoroethylene Polymers 0.000 description 3
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 3
- 239000004810 polytetrafluoroethylene Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000013007 heat curing Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910018182 Al—Cu Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910008599 TiW Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000005361 soda-lime glass Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
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Abstract
【解決方法】互いに相対向する第1の主面及び第2の主面を有し、厚さ方向に貫通して前記第1の主面及び前記第2の主面を連通するようにして貫通孔が形成されてなる半導体基板と、前記半導体基板の前記第1の主面上に形成された第1の絶縁層及び第1の導電層と、前記貫通孔の内壁面上から前記半導体基板の前記第2の主面上にかけて連続的に形成された第2の絶縁層と、前記第1の導電層に当接するとともに、前記第2の絶縁層上において、前記貫通孔の前記内壁面上から前記半導体基板の前記第2の主面上にかけて連続的に形成されてなる第2の導電層とを具え、前記貫通孔内の、前記半導体基板の前記第1の主面側の端部において空隙部を有するようにして、前記貫通孔を充填材で埋設して半導体装置を構成する。
【選択図】図1
Description
前記第1の絶縁層上に第1の導電層を形成する工程と、前記半導体基板の、前記第1の主面と相対向する第2の主面側から前記第1の主面側へ向けて貫通孔を形成し、前記第1の絶縁層を露出させる工程と、前記貫通孔の内壁面上及び前記半導体基板の前記第2の主面上に第2の絶縁層を形成する工程と、前記第1の絶縁層及び前記第2の絶縁層部分を除去し、前記貫通孔内に前記第1の導電層を露出させる工程と、前記第1の導電層に当接し、前記貫通孔及び前記第2の主面の前記第2の絶縁層上に第2の導電層を形成する工程と、前記半導体基板の前記第1の主面側において、前記第2の導電層との間に空隙部を有し、前記貫通孔内の前記第2の導電層上に充填材を設ける工程と、を具えることを特徴とする、半導体装置の製造方法に関する。
図1は、第1の実施形態に係る半導体装置の構成を示す断面図である。
次に、実施形態に係る半導体装置の製造方法について説明する。本態様では、図1に示すような半導体装置1の製造方法について具体的に説明する。図3(a)〜(f)は、本態様における半導体装置の製造方法の各工程を示す断面図である。
次いで、実施形態に係るカメラモジュールについて説明する。図4は、本態様におけるカメラモジュールの概略構成を示す断面図である。
Claims (5)
- 互いに相対向する第1の主面及び第2の主面を有し、厚さ方向に貫通して前記第1の主面及び前記第2の主面を連通するようにして貫通孔が形成されてなる半導体基板と、
前記半導体基板の前記第1の主面上において、前記貫通孔の前記第1の主面側を開口するようにして形成されてなる第1の絶縁層と、
前記第1の絶縁層上に、前記貫通孔の前記第1の主面側の前記開口を覆うように形成された第1の導電層と、
前記貫通孔の内壁面上及び前記半導体基板の前記第2の主面上に形成された第2の絶縁層と、
前記第1の導電層に当接し、前記貫通孔及び前記第2の主面の前記第2の絶縁層上に形成された第2の導電層と、
前記半導体基板の前記第1の主面側において、前記第2の導電層との間に空隙部を有し、前記貫通孔内の前記第2の導電層上に設けられた充填材と、
を具えることを特徴とする、半導体装置。 - 前記充填材は絶縁材料であって、前記貫通孔から前記半導体基板の前記第2の主面上に延在し、前記第2の絶縁層及び前記第2の導電層を覆うようにして設けられたことを特徴とする、請求項1に記載の半導体装置。
- 前記充填材は導電性材料であって、前記半導体基板の前記第2の主面上において、前記第2の導電層と接触するようにして設けられていることを特徴とする、請求項1に記載の半導体装置。
- 半導体基板の第1の主面上に第1の絶縁層を形成する工程と、
前記第1の絶縁層上に第1の導電層を形成する工程と、
前記半導体基板の、前記第1の主面と相対向する第2の主面側から前記第1の主面側へ向けて貫通孔を形成し、前記第1の絶縁層を露出させる工程と、
前記貫通孔の内壁面上及び前記半導体基板の前記第2の主面上に第2の絶縁層を形成する工程と、
前記第1の絶縁層及び前記第2の絶縁層部分を除去し、前記貫通孔内に前記第1の導電層を露出させる工程と、
前記第1の導電層に当接し、前記貫通孔及び前記第2の主面の前記第2の絶縁層上に第2の導電層を形成する工程と、
前記半導体基板の前記第1の主面側において、前記第2の導電層との間に空隙部を有し、前記貫通孔内の前記第2の導電層上に充填材を設ける工程と、
を具えることを特徴とする、半導体装置の製造方法。 - 請求項1〜3のいずれか一に記載の半導体装置をセンサーを含むセンサーモジュールと、
前記半導体装置における前記半導体基板の前記第1の主面上に設けられ、前記第1の導電層と電気的に接続されてなる受光部、前記受光部上に配置された光透過性保護部材、及び集光レンズユニットを含むレンズモジュールと、
を具えることを特徴とする、カメラモジュール。
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US12/539,037 US8426977B2 (en) | 2008-08-12 | 2009-08-11 | Semiconductor apparatus, manufacturing method of semiconductor apparatus, and camera module |
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