JP2009535820A5 - - Google Patents

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Publication number
JP2009535820A5
JP2009535820A5 JP2009507865A JP2009507865A JP2009535820A5 JP 2009535820 A5 JP2009535820 A5 JP 2009535820A5 JP 2009507865 A JP2009507865 A JP 2009507865A JP 2009507865 A JP2009507865 A JP 2009507865A JP 2009535820 A5 JP2009535820 A5 JP 2009535820A5
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JP
Japan
Prior art keywords
forming
gate
opening
dimension
fin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009507865A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009535820A (ja
JP5208918B2 (ja
Filing date
Publication date
Priority claimed from US11/380,530 external-priority patent/US7442590B2/en
Application filed filed Critical
Publication of JP2009535820A publication Critical patent/JP2009535820A/ja
Publication of JP2009535820A5 publication Critical patent/JP2009535820A5/ja
Application granted granted Critical
Publication of JP5208918B2 publication Critical patent/JP5208918B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009507865A 2006-04-27 2007-03-14 フィンを有する半導体デバイスを形成する方法 Active JP5208918B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/380,530 US7442590B2 (en) 2006-04-27 2006-04-27 Method for forming a semiconductor device having a fin and structure thereof
US11/380,530 2006-04-27
PCT/US2007/063966 WO2007127533A2 (en) 2006-04-27 2007-03-14 Method for forming a semiconductor device having a fin and structure thereof

Publications (3)

Publication Number Publication Date
JP2009535820A JP2009535820A (ja) 2009-10-01
JP2009535820A5 true JP2009535820A5 (enExample) 2010-04-30
JP5208918B2 JP5208918B2 (ja) 2013-06-12

Family

ID=38648827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009507865A Active JP5208918B2 (ja) 2006-04-27 2007-03-14 フィンを有する半導体デバイスを形成する方法

Country Status (6)

Country Link
US (1) US7442590B2 (enExample)
JP (1) JP5208918B2 (enExample)
KR (1) KR20090005066A (enExample)
CN (1) CN101432877B (enExample)
TW (1) TWI404206B (enExample)
WO (1) WO2007127533A2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6267958B1 (en) 1995-07-27 2001-07-31 Genentech, Inc. Protein formulation
US8202780B2 (en) * 2009-07-31 2012-06-19 International Business Machines Corporation Method for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regions
JP5569243B2 (ja) * 2010-08-09 2014-08-13 ソニー株式会社 半導体装置及びその製造方法
US8901665B2 (en) * 2011-12-22 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure for semiconductor device
US8766363B2 (en) 2012-11-07 2014-07-01 International Business Machines Corporation Method and structure for forming a localized SOI finFET
US8987823B2 (en) 2012-11-07 2015-03-24 International Business Machines Corporation Method and structure for forming a localized SOI finFET
US20140167162A1 (en) 2012-12-13 2014-06-19 International Business Machines Corporation Finfet with merge-free fins
US8981496B2 (en) * 2013-02-27 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate and gate contact structure for FinFET
US9018054B2 (en) 2013-03-15 2015-04-28 Applied Materials, Inc. Metal gate structures for field effect transistors and method of fabrication
US8969155B2 (en) 2013-05-10 2015-03-03 International Business Machines Corporation Fin structure with varying isolation thickness
US9287372B2 (en) * 2013-12-27 2016-03-15 Taiwan Semiconductor Manufacturing Company Limited Method of forming trench on FinFET and FinFET thereof
US9679985B1 (en) * 2016-06-20 2017-06-13 Globalfoundries Inc. Devices and methods of improving device performance through gate cut last process
CN109427664B (zh) * 2017-08-24 2021-08-06 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11973143B2 (en) 2019-03-28 2024-04-30 Intel Corporation Source or drain structures for germanium N-channel devices

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6800905B2 (en) * 2001-12-14 2004-10-05 International Business Machines Corporation Implanted asymmetric doped polysilicon gate FinFET
US6803631B2 (en) * 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US6855582B1 (en) * 2003-06-12 2005-02-15 Advanced Micro Devices, Inc. FinFET gate formation using reverse trim and oxide polish
US6855989B1 (en) * 2003-10-01 2005-02-15 Advanced Micro Devices, Inc. Damascene finfet gate with selective metal interdiffusion
US6951783B2 (en) * 2003-10-28 2005-10-04 Freescale Semiconductor, Inc. Confined spacers for double gate transistor semiconductor fabrication process
US7041542B2 (en) * 2004-01-12 2006-05-09 Advanced Micro Devices, Inc. Damascene tri-gate FinFET
US6936516B1 (en) * 2004-01-12 2005-08-30 Advanced Micro Devices, Inc. Replacement gate strained silicon finFET process
JP4796329B2 (ja) * 2004-05-25 2011-10-19 三星電子株式会社 マルチ−ブリッジチャンネル型ｍｏｓトランジスタの製造方法

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