TWI404206B - 形成具有鰭狀物之半導體裝置之方法及其結構 - Google Patents

形成具有鰭狀物之半導體裝置之方法及其結構 Download PDF

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Publication number
TWI404206B
TWI404206B TW096109944A TW96109944A TWI404206B TW I404206 B TWI404206 B TW I404206B TW 096109944 A TW096109944 A TW 096109944A TW 96109944 A TW96109944 A TW 96109944A TW I404206 B TWI404206 B TW I404206B
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TW
Taiwan
Prior art keywords
forming
layer
gate
passivation layer
opening
Prior art date
Application number
TW096109944A
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English (en)
Chinese (zh)
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TW200742070A (en
Inventor
Marius K Orlowski
Original Assignee
Freescale Semiconductor Inc
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Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200742070A publication Critical patent/TW200742070A/zh
Application granted granted Critical
Publication of TWI404206B publication Critical patent/TWI404206B/zh

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/62Fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/017Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
TW096109944A 2006-04-27 2007-03-22 形成具有鰭狀物之半導體裝置之方法及其結構 TWI404206B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/380,530 US7442590B2 (en) 2006-04-27 2006-04-27 Method for forming a semiconductor device having a fin and structure thereof

Publications (2)

Publication Number Publication Date
TW200742070A TW200742070A (en) 2007-11-01
TWI404206B true TWI404206B (zh) 2013-08-01

Family

ID=38648827

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096109944A TWI404206B (zh) 2006-04-27 2007-03-22 形成具有鰭狀物之半導體裝置之方法及其結構

Country Status (6)

Country Link
US (1) US7442590B2 (enExample)
JP (1) JP5208918B2 (enExample)
KR (1) KR20090005066A (enExample)
CN (1) CN101432877B (enExample)
TW (1) TWI404206B (enExample)
WO (1) WO2007127533A2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6267958B1 (en) 1995-07-27 2001-07-31 Genentech, Inc. Protein formulation
US8202780B2 (en) * 2009-07-31 2012-06-19 International Business Machines Corporation Method for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regions
JP5569243B2 (ja) * 2010-08-09 2014-08-13 ソニー株式会社 半導体装置及びその製造方法
US8901665B2 (en) * 2011-12-22 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure for semiconductor device
US8766363B2 (en) 2012-11-07 2014-07-01 International Business Machines Corporation Method and structure for forming a localized SOI finFET
US8987823B2 (en) 2012-11-07 2015-03-24 International Business Machines Corporation Method and structure for forming a localized SOI finFET
US20140167162A1 (en) 2012-12-13 2014-06-19 International Business Machines Corporation Finfet with merge-free fins
US8981496B2 (en) * 2013-02-27 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate and gate contact structure for FinFET
US9018054B2 (en) 2013-03-15 2015-04-28 Applied Materials, Inc. Metal gate structures for field effect transistors and method of fabrication
US8969155B2 (en) 2013-05-10 2015-03-03 International Business Machines Corporation Fin structure with varying isolation thickness
US9287372B2 (en) * 2013-12-27 2016-03-15 Taiwan Semiconductor Manufacturing Company Limited Method of forming trench on FinFET and FinFET thereof
US9679985B1 (en) * 2016-06-20 2017-06-13 Globalfoundries Inc. Devices and methods of improving device performance through gate cut last process
CN109427664B (zh) * 2017-08-24 2021-08-06 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11973143B2 (en) 2019-03-28 2024-04-30 Intel Corporation Source or drain structures for germanium N-channel devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525403B2 (en) * 2000-09-28 2003-02-25 Kabushiki Kaisha Toshiba Semiconductor device having MIS field effect transistors or three-dimensional structure
US6800905B2 (en) * 2001-12-14 2004-10-05 International Business Machines Corporation Implanted asymmetric doped polysilicon gate FinFET
US6803631B2 (en) * 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US6855989B1 (en) * 2003-10-01 2005-02-15 Advanced Micro Devices, Inc. Damascene finfet gate with selective metal interdiffusion
US6855582B1 (en) * 2003-06-12 2005-02-15 Advanced Micro Devices, Inc. FinFET gate formation using reverse trim and oxide polish

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6951783B2 (en) * 2003-10-28 2005-10-04 Freescale Semiconductor, Inc. Confined spacers for double gate transistor semiconductor fabrication process
US7041542B2 (en) * 2004-01-12 2006-05-09 Advanced Micro Devices, Inc. Damascene tri-gate FinFET
US6936516B1 (en) * 2004-01-12 2005-08-30 Advanced Micro Devices, Inc. Replacement gate strained silicon finFET process
JP4796329B2 (ja) * 2004-05-25 2011-10-19 三星電子株式会社 マルチ−ブリッジチャンネル型mosトランジスタの製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525403B2 (en) * 2000-09-28 2003-02-25 Kabushiki Kaisha Toshiba Semiconductor device having MIS field effect transistors or three-dimensional structure
US6800905B2 (en) * 2001-12-14 2004-10-05 International Business Machines Corporation Implanted asymmetric doped polysilicon gate FinFET
US6803631B2 (en) * 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US6855582B1 (en) * 2003-06-12 2005-02-15 Advanced Micro Devices, Inc. FinFET gate formation using reverse trim and oxide polish
US6855989B1 (en) * 2003-10-01 2005-02-15 Advanced Micro Devices, Inc. Damascene finfet gate with selective metal interdiffusion

Also Published As

Publication number Publication date
JP2009535820A (ja) 2009-10-01
WO2007127533A3 (en) 2008-06-26
CN101432877A (zh) 2009-05-13
US20070254435A1 (en) 2007-11-01
TW200742070A (en) 2007-11-01
JP5208918B2 (ja) 2013-06-12
CN101432877B (zh) 2011-09-28
KR20090005066A (ko) 2009-01-12
WO2007127533A2 (en) 2007-11-08
US7442590B2 (en) 2008-10-28

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