JP2009525515A5 - - Google Patents

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Publication number
JP2009525515A5
JP2009525515A5 JP2008551748A JP2008551748A JP2009525515A5 JP 2009525515 A5 JP2009525515 A5 JP 2009525515A5 JP 2008551748 A JP2008551748 A JP 2008551748A JP 2008551748 A JP2008551748 A JP 2008551748A JP 2009525515 A5 JP2009525515 A5 JP 2009525515A5
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JP
Japan
Prior art keywords
data
bus
clk
line
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008551748A
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English (en)
Japanese (ja)
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JP2009525515A (ja
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Publication date
Priority claimed from DE102006004346A external-priority patent/DE102006004346A1/de
Application filed filed Critical
Publication of JP2009525515A publication Critical patent/JP2009525515A/ja
Publication of JP2009525515A5 publication Critical patent/JP2009525515A5/ja
Pending legal-status Critical Current

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JP2008551748A 2006-01-30 2007-01-11 インタラプティブルクロックを用いたデータバスインタフェース Pending JP2009525515A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102006004346A DE102006004346A1 (de) 2006-01-30 2006-01-30 Datenbusschnittstelle mit abschaltbarem Takt
PCT/EP2007/050261 WO2007085532A1 (en) 2006-01-30 2007-01-11 Data bus interface with interruptible clock

Publications (2)

Publication Number Publication Date
JP2009525515A JP2009525515A (ja) 2009-07-09
JP2009525515A5 true JP2009525515A5 (https=) 2010-02-12

Family

ID=37907812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008551748A Pending JP2009525515A (ja) 2006-01-30 2007-01-11 インタラプティブルクロックを用いたデータバスインタフェース

Country Status (8)

Country Link
US (1) US7984214B2 (https=)
EP (1) EP1979822B1 (https=)
JP (1) JP2009525515A (https=)
KR (1) KR101336105B1 (https=)
CN (1) CN101371234B (https=)
DE (2) DE102006004346A1 (https=)
TW (1) TWI422195B (https=)
WO (1) WO2007085532A1 (https=)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5217982B2 (ja) * 2008-12-04 2013-06-19 ソニー株式会社 情報処理装置および方法、並びにプログラム
FR2939926B1 (fr) * 2008-12-17 2010-12-10 St Microelectronics Rousset Transmission sur bus i2c
CN102117254B (zh) * 2011-01-17 2012-11-21 青岛海信日立空调系统有限公司 基于嵌入式系统实现数据异步接收的方法
CN102289278B (zh) * 2011-08-09 2013-11-06 西安华芯半导体有限公司 超低功耗接口
CN102622325B (zh) * 2011-12-23 2014-12-24 苏州华芯微电子股份有限公司 I2c总线启动与停止电路结构
GB2493416B (en) * 2012-05-24 2014-04-23 Broadcom Corp Apparatus and method for synchronising signals
KR20140035771A (ko) * 2012-09-14 2014-03-24 삼성전자주식회사 임베디드 멀티미디어 카드, 상기 임베디드 멀티미디어 카드를 제어하는 호스트, 및 그 동작방법
KR101932920B1 (ko) * 2012-09-14 2019-03-18 삼성전자 주식회사 비휘발성 메모리 카드를 제어하는 호스트, 이를 포함하는 시스템 및 이의 동작 방법
DE102012110766A1 (de) * 2012-11-09 2014-05-15 MAQUET GmbH Instrumentenhalter zum Befestigen eines medizinischen Instrumentes an einem Gelenkarm
US9910819B2 (en) * 2013-03-11 2018-03-06 Microchip Technology Incorporated Two-wire serial interface and protocol
US9690725B2 (en) 2014-01-14 2017-06-27 Qualcomm Incorporated Camera control interface extension with in-band interrupt
US9678828B2 (en) 2013-10-09 2017-06-13 QUAULCOMM Incorporated Error detection capability over CCIe protocol
US9996488B2 (en) 2013-09-09 2018-06-12 Qualcomm Incorporated I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator
US10353837B2 (en) 2013-09-09 2019-07-16 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
US9684624B2 (en) * 2014-01-14 2017-06-20 Qualcomm Incorporated Receive clock calibration for a serial bus
DE102014206752B4 (de) * 2014-04-08 2021-08-12 Robert Bosch Gmbh Bestimmung des Zustands eines I2C-Busses
US10997114B2 (en) * 2018-06-08 2021-05-04 Qualcomm Incorporated Vector decoding in time-constrained double data rate interface
FR3100349B1 (fr) * 2019-08-28 2022-07-08 Stmicroelectronics Grand Ouest Sas Communication sur bus I2C
FR3109227B1 (fr) * 2020-04-14 2022-05-06 St Microelectronics Alps Sas Contrôleur d’interruption et procédé de gestion d’un tel contrôleur
KR20240120525A (ko) * 2023-01-31 2024-08-07 엘지디스플레이 주식회사 표시 장치

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4545030A (en) * 1982-09-28 1985-10-01 The John Hopkins University Synchronous clock stopper for microprocessor
JP2676966B2 (ja) * 1990-03-16 1997-11-17 日本電気株式会社 シングルチップマイクロコンピュータ
GB2246687B (en) * 1990-04-06 1994-04-27 Plessey Co Ltd Improvements relating to data transmission systems
JPH06202762A (ja) * 1992-10-30 1994-07-22 Nippon Motorola Ltd ライトデータ保護機能付きリセット信号発生回路
US5598112A (en) * 1995-05-26 1997-01-28 National Semiconductor Corporation Circuit for generating a demand-based gated clock
KR0184136B1 (ko) * 1996-06-03 1999-05-15 구자홍 범용 마이컴을 이용한 아이 스퀘어 씨 통신 장치
US5878234A (en) * 1996-09-10 1999-03-02 Sierra Wireless, Inc. Low power serial protocol translator for use in multi-circuit board electronic systems
DE19642265C1 (de) * 1996-10-11 1998-01-29 Becker Gmbh Verfahren zum Betreten und Verlassen eines Stromsparbetriebs eines Teilnehmers in einem ringförmigen Kommunikationsnetz
US6023743A (en) * 1997-06-10 2000-02-08 International Business Machines Corporation System and method for arbitrating interrupts on a daisy chained architected bus
US6032178A (en) * 1998-01-12 2000-02-29 Siemens Aktiengesellschaft Method and arrangement for data transmission between units on a bus system selectively transmitting data in one of a first and a second data transmission configurations
US6049883A (en) * 1998-04-01 2000-04-11 Tjandrasuwita; Ignatius B. Data path clock skew management in a dynamic power management environment
US6202104B1 (en) * 1998-07-28 2001-03-13 Siemens Aktiengesellschaft Processor having a clock driven CPU with static design
DE19844936C2 (de) * 1998-09-30 2001-02-01 Siemens Ag Schaltung zur Erzeugung eines Ausgangssignals in Abhängigkeit von zwei Eingangssignalen
US6311285B1 (en) * 1999-04-27 2001-10-30 Intel Corporation Method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency
US6232820B1 (en) * 1999-06-14 2001-05-15 Intel Corporation Method and apparatus for dynamic clock gating
US6530029B1 (en) * 1999-09-23 2003-03-04 National Semiconductor Corporation I2C/SMBus start-stop detecting circuit that reduces the likelihood of stalling the bus due to glitches on the data line
JP2001267897A (ja) * 2000-03-17 2001-09-28 Oki Electric Ind Co Ltd 遅延装置および方法
US7069359B1 (en) * 2000-04-03 2006-06-27 Intel Corporation Circuit and technique to stall the communication of data over a double pumped bus
US6745337B1 (en) * 2000-09-29 2004-06-01 Intel Corporation Glitch detection circuit for outputting a signal indicative of a glitch on a strobe signal and initializing an edge detection circuit in response to a control signal
US6920572B2 (en) * 2000-11-15 2005-07-19 Texas Instruments Incorporated Unanimous voting for disabling of shared component clocking in a multicore DSP device
JP2002318646A (ja) * 2001-04-24 2002-10-31 Sony Corp 情報処理装置および方法
US6799233B1 (en) * 2001-06-29 2004-09-28 Koninklijke Philips Electronics N.V. Generalized I2C slave transmitter/receiver state machine
JP3844120B2 (ja) * 2001-10-19 2006-11-08 株式会社ルネサステクノロジ 半導体装置
US6529442B1 (en) * 2002-01-08 2003-03-04 Intel Corporation Memory controller with AC power reduction through non-return-to-idle of address and control signals
US20030135676A1 (en) * 2002-01-17 2003-07-17 Koninklijke Philips Electronics N.V. Low-power bus interface
JP4219601B2 (ja) * 2002-03-01 2009-02-04 富士通マイクロエレクトロニクス株式会社 情報処理装置
US6968472B2 (en) * 2002-04-22 2005-11-22 Silicon Labs Cp. Inc. Serial data interface
FR2839827B1 (fr) * 2002-05-14 2005-07-15 St Microelectronics Sa Circuit de detection de depart, circuit de detection d'arret, et circuit de detection de donnees transmises selon le protocole iic
JP4207151B2 (ja) * 2003-03-17 2009-01-14 セイコーエプソン株式会社 非同期プロセッサを備えた通信装置及びその通信方法
JP4411579B2 (ja) * 2003-04-07 2010-02-10 日本電気株式会社 バスシステム
KR100591524B1 (ko) * 2004-05-14 2006-06-19 삼성전자주식회사 버스 구조하에서 다이나믹 클록 게이팅이 가능한 슬레이브장치 및 그 동작방법
DE102005041895B4 (de) 2005-09-03 2010-12-09 Audi Ag Steuergerät und Verfahren zum Steuern eines Abschaltvorgangs eines Steuergeräts
US7401242B2 (en) * 2005-09-27 2008-07-15 International Business Machines Corporation Dynamic power management in a processor design

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