DE602007006424D1 - Datenbus-schnittstelle mit unterbrechbarer uhr - Google Patents

Datenbus-schnittstelle mit unterbrechbarer uhr

Info

Publication number
DE602007006424D1
DE602007006424D1 DE602007006424T DE602007006424T DE602007006424D1 DE 602007006424 D1 DE602007006424 D1 DE 602007006424D1 DE 602007006424 T DE602007006424 T DE 602007006424T DE 602007006424 T DE602007006424 T DE 602007006424T DE 602007006424 D1 DE602007006424 D1 DE 602007006424D1
Authority
DE
Germany
Prior art keywords
interruptable
clock
data bus
bus interface
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007006424T
Other languages
English (en)
Inventor
Friedrich Heizmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson Licensing SAS
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Publication of DE602007006424D1 publication Critical patent/DE602007006424D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/068—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection by sampling faster than the nominal bit rate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
DE602007006424T 2006-01-30 2007-01-11 Datenbus-schnittstelle mit unterbrechbarer uhr Active DE602007006424D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102006004346A DE102006004346A1 (de) 2006-01-30 2006-01-30 Datenbusschnittstelle mit abschaltbarem Takt
PCT/EP2007/050261 WO2007085532A1 (en) 2006-01-30 2007-01-11 Data bus interface with interruptible clock

Publications (1)

Publication Number Publication Date
DE602007006424D1 true DE602007006424D1 (de) 2010-06-24

Family

ID=37907812

Family Applications (2)

Application Number Title Priority Date Filing Date
DE102006004346A Withdrawn DE102006004346A1 (de) 2006-01-30 2006-01-30 Datenbusschnittstelle mit abschaltbarem Takt
DE602007006424T Active DE602007006424D1 (de) 2006-01-30 2007-01-11 Datenbus-schnittstelle mit unterbrechbarer uhr

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE102006004346A Withdrawn DE102006004346A1 (de) 2006-01-30 2006-01-30 Datenbusschnittstelle mit abschaltbarem Takt

Country Status (8)

Country Link
US (1) US7984214B2 (de)
EP (1) EP1979822B1 (de)
JP (1) JP2009525515A (de)
KR (1) KR101336105B1 (de)
CN (1) CN101371234B (de)
DE (2) DE102006004346A1 (de)
TW (1) TWI422195B (de)
WO (1) WO2007085532A1 (de)

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FR2939926B1 (fr) * 2008-12-17 2010-12-10 St Microelectronics Rousset Transmission sur bus i2c
CN102117254B (zh) * 2011-01-17 2012-11-21 青岛海信日立空调系统有限公司 基于嵌入式系统实现数据异步接收的方法
CN102289278B (zh) * 2011-08-09 2013-11-06 西安华芯半导体有限公司 超低功耗接口
CN102622325B (zh) * 2011-12-23 2014-12-24 苏州华芯微电子股份有限公司 I2c总线启动与停止电路结构
GB2493416B (en) 2012-05-24 2014-04-23 Broadcom Corp Apparatus and method for synchronising signals
KR101932920B1 (ko) 2012-09-14 2019-03-18 삼성전자 주식회사 비휘발성 메모리 카드를 제어하는 호스트, 이를 포함하는 시스템 및 이의 동작 방법
KR20140035771A (ko) * 2012-09-14 2014-03-24 삼성전자주식회사 임베디드 멀티미디어 카드, 상기 임베디드 멀티미디어 카드를 제어하는 호스트, 및 그 동작방법
DE102012110766A1 (de) * 2012-11-09 2014-05-15 MAQUET GmbH Instrumentenhalter zum Befestigen eines medizinischen Instrumentes an einem Gelenkarm
US9910819B2 (en) * 2013-03-11 2018-03-06 Microchip Technology Incorporated Two-wire serial interface and protocol
US10353837B2 (en) 2013-09-09 2019-07-16 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
US9690725B2 (en) 2014-01-14 2017-06-27 Qualcomm Incorporated Camera control interface extension with in-band interrupt
US9996488B2 (en) 2013-09-09 2018-06-12 Qualcomm Incorporated I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator
EP3055929A1 (de) 2013-10-09 2016-08-17 Qualcomm Incorporated Fehlererkennungsfähigkeit über ccie-protokoll
US9684624B2 (en) * 2014-01-14 2017-06-20 Qualcomm Incorporated Receive clock calibration for a serial bus
DE102014206752B4 (de) * 2014-04-08 2021-08-12 Robert Bosch Gmbh Bestimmung des Zustands eines I2C-Busses
US10997114B2 (en) * 2018-06-08 2021-05-04 Qualcomm Incorporated Vector decoding in time-constrained double data rate interface
FR3100349B1 (fr) * 2019-08-28 2022-07-08 Stmicroelectronics Grand Ouest Sas Communication sur bus I2C
FR3109227B1 (fr) * 2020-04-14 2022-05-06 St Microelectronics Alps Sas Contrôleur d’interruption et procédé de gestion d’un tel contrôleur

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Also Published As

Publication number Publication date
KR20080091341A (ko) 2008-10-10
KR101336105B1 (ko) 2013-12-04
TWI422195B (zh) 2014-01-01
JP2009525515A (ja) 2009-07-09
EP1979822B1 (de) 2010-05-12
CN101371234B (zh) 2011-09-21
US7984214B2 (en) 2011-07-19
US20090024781A1 (en) 2009-01-22
DE102006004346A1 (de) 2007-10-18
WO2007085532A1 (en) 2007-08-02
CN101371234A (zh) 2009-02-18
EP1979822A1 (de) 2008-10-15
TW200733655A (en) 2007-09-01

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Legal Events

Date Code Title Description
8320 Willingness to grant licences declared (paragraph 23)
8364 No opposition during term of opposition