JP2009517885A - 傾斜式プレアモルファス化による歪みトランジスタの結晶欠陥低減化技術 - Google Patents
傾斜式プレアモルファス化による歪みトランジスタの結晶欠陥低減化技術 Download PDFInfo
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- JP2009517885A JP2009517885A JP2008543308A JP2008543308A JP2009517885A JP 2009517885 A JP2009517885 A JP 2009517885A JP 2008543308 A JP2008543308 A JP 2008543308A JP 2008543308 A JP2008543308 A JP 2008543308A JP 2009517885 A JP2009517885 A JP 2009517885A
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Abstract
Description
加えて、ゲート絶縁層に対して垂直のPN接合の位置はさらに、漏れ電流制御の点でクリティカルなデザイン基準を表すことになる。チャネル長を縮小するには、通常、ゲート絶縁層およびチャネル領域によって形成されるインターフェースに対してドレインおよびソース領域の深さも低くしなければならず、これにより洗練されたインプラント技術が要求されるからである。別のアプローチによれば、隆起したドレインおよびソース領域と呼ばれるエピタキシャル成長した領域が、ゲート電極に対して特定のオフセットを備えて形成され、この隆起したドレインおよびソース領域の導電性が増加される一方で、ゲート絶縁層に対して浅いPN接合が維持される。
例えば、チャネル領域に引張歪みを生成することで電子の移動度が増加する。ここでは、引張歪みの大きさおよび方向に応じて、移動度を50%あるいはそれ以上増加させることができ、これに対応して導電性度が増加し得る。他方では、チャネル領域の圧縮歪みにより正孔移動度が増加し、これにより、P型トランジスタのパフォーマンスを強化する可能性が与えられる。集積回路の製造に応力や歪み技術を導入することは、将来のデバイス世代にとって非常に有望なアプローチである。その理由は、例えば、歪みのあるシリコンは、「新たな」種類のシリコン材料として考えられ、これにより、高額な半導体材料を必要とせずに、高速で強力な半導体デバイスの製造が可能になる一方で、十分に確立された多くの製造技術を依然として用いることができる。
別のアプローチにおいては、PMOSトランジスタの正孔移動度は、トランジスタのソースおよびドレイン領域に歪みのあるシリコン/ゲルマニウム層を形成することで強化することができる。ここでは、圧縮歪みのあるドレインおよびソース領域は、隣接するシリコンチャネル領域に一軸性の歪みを生成する。このために、PMOSトランジスタのドレインおよびソース領域には選択的にリセスが設けられる一方、NMOSトランジスタはマスキングされ、その後、シリコン/ゲルマニウム層がエピタキシャル成長によりPMOSトランジスタに選択的に形成される。この技術は、PMOSトランジスタと、よってCMOSデバイス全体のパフォーマンスゲインの点では著しい利点を与えるが、PMOSトランジスタとNMOSトランジスタのパフォーマンスゲインにおける差分のバランスをとる適切な設計を用いる必要がある。
次に、適切な誘電材料が蒸着および/または酸化により形成され、続いて、適切なゲート電極材料が蒸着され、次に、両方の層は次いで高度なフォトリソグラフィおよびエッチ技術に基づいてパターニングされる。続いて、十分に確立されたプラズマエンハンスト化学気相蒸着(PECVD:Plasma Enhanced chemical Vapor Deposition)技術に基づいてライナ106が形成される。このライナは、プロセス要件ならびにストラテジーに応じて、十分に確立されたインプランテーション技術に基づいてドープ領域107を形成するオフセットスペーサとして機能する。さらに、PチャネルトランジスタまたはNチャネルトランジスタが形成されるかどうかに応じて、P型ドーパントまたはN型ドーパントを含むドープ領域107の形成前または形成後に、アモルファス化インプランテーションプロセス(amorphization implantation process)108が実行される。このために、十分に確立されたレシピに基づいて、対象のインプラント種に対して適切なドーズ量ならびにエネルギーが選択される。例えば、アモルファス化インプランテーション108には、キセノン、ゲルマニウム、およびその他の重イオンが適切とされる。その後、対応のスペーサ層が引張応力や圧縮応力といった特定の種類の固有応力を示すように、半導体デバイス100の上方にスペーサ層が形成され、層の蒸着後に、または、その後の、異方性エッチ技術に基づきスペーサ層をそれぞれのサイドウォールスペーサへパターニング後に、実質的にアモルファス化した領域112を再結晶化するように、アニールプロセスが行われる。
Claims (11)
- 初期において結晶性である半導体層(203、303)に実質的にアモルファス化した領域(212、312)を形成するステップを有し、前記半導体層(203、303)はゲート電極(204、304)に隣接するとともにその下方に延びており、前記ゲート電極(204、304)は傾斜インプランテーションプロセス(208、308P、308N)により前記半導体層(202、303)の上方に形成されているものであり、
少なくとも前記半導体層(202、203)の一部の上方に特定の固有応力を有する応力のかけられた層(209、309)を形成するステップを有し、前記層(209、309)を形成することで前記半導体層(202、303)へ応力の転移がなされ、
前記応力層(209、309)の存在下で、熱処理(223)を実行することによって、前記実質的にアモルファス化した領域(212、312)を再結晶化するステップを有する方法。 - 前記応力層(209、309)を形成するステップは、前記特定の応力を備えたスペーサ層を共形に蒸着するステップと、前記スペーサ層を異方性エッチングするステップと、を含み、このようなステップがなされることで、前記応力層(209、309)として前記ゲート電極(204、304)のサイドウォールに第1スペーサ(209、309)が形成される、請求項1記載の方法。
- 前記傾斜インプランテーションプロセス(208、308P、308N)は、前記第1スペーサ(209、309)の形成後に実行される、請求項2記載の方法。
- 前記熱処理を実行する前に、前記特定の固有応力を有する第2スペーサ(211、311)を前記第1スペーサ(209、309)に隣接して形成するステップをさらに含む、請求項2または3記載の方法。
- 少なくとも1つの前記第1スペーサ(209、309)および第2スペーサ(211、311)を形成後に、前記半導体層(202、303)にドーパント種をインプラントする(220、222)ステップをさらに含み、前記熱処理(223)は前記ドーパント種のインプラント(220、222)後に実行される、請求項4記載の方法。
- 前記半導体層(203、303)にドレインおよびソース領域(207、307)を形成するように、前記実質的にアモルファス化した領域にドーパント種をインプラントする(220、222)さらなるステップを含む、請求項1記載の方法。
- 初期において実質的に結晶性である半導体層(303)の上方に形成された第1ゲート電極に隣接するとともにその下方に拡張する第1の実質的にアモルファス化下領域(312)を形成するステップと、
前記半導体層(303)の上方に形成された第2ゲート電極(304)に隣接するとともにその下方に拡張する第2の実質的にアモルファス化した領域(312)を形成するステップと、
前記第1ゲート電極(304)のサイドウォールに第1の種類の応力を有する第1スペーサ(309)を形成するステップと、
前記第2ゲート電極(304)のサイドウォールに前記第1の種類以外の第2の種類の応力を有する第2スペーサ(319S)を形成するステップと、
前記第1および第2の応力のかけられたスペーサ(309、319S)の存在下で、熱処理(323)を実行することによって前記第1および第2の実質的にアモルファス化した領域(312)を再結晶化するステップと、を含む方法。 - 前記第1および第2の実質的にアモルファス化した領域(312)を形成するステップは、傾斜インプランテーションプロセス(308N、308P)を実行するステップを含む、請求項7記載の方法。
- 前記傾斜インプランテーションプロセス(308N、308P)は、前記第1の実質的にアモルファス化した領域(312)を形成する第1のインプランテーションプロセス(308N)と、前記第2の実質的にアモルファス化した領域(312)を形成する第2のインプランテーションプロセス(308P)を含む、請求項8記載の方法。
- 前記第1および第2の実質的にアモルファス化した領域(312)は、前記第1および第2スペーサ(309、319S)の形成後に形成される、請求項7記載の方法。
- 前記第1および第2スペーサ(309)を形成するステップは、前記第1および第2ゲート電極(304)に前記第1スペーサ(309)を共通に形成し、前記第1スペーサ(309)を前記第2ゲート電極(304)から選択的に除去し、前記第1および第2ゲート電極(304)の上方に前記第2の種類の応力を有するスペーサ層(319)を形成し、前記スペーサ層(319)から前記第2スペーサ(319S)を形成し、前記スペーサ層(319)からの残留物を前記第1ゲート電極(304)から選択的に除去する、請求項7記載の方法。
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US11/530,722 US20070123010A1 (en) | 2005-11-30 | 2006-09-11 | Technique for reducing crystal defects in strained transistors by tilted preamorphization |
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JP2011501437A (ja) * | 2007-10-30 | 2011-01-06 | シノプシス, インコーポレイテッド | 半導体基板における格子欠陥の抑制方法 |
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US20070123010A1 (en) | 2007-05-31 |
CN101322228B (zh) | 2012-07-25 |
TW200746312A (en) | 2007-12-16 |
KR20080073352A (ko) | 2008-08-08 |
CN101322228A (zh) | 2008-12-10 |
EP1961039A1 (en) | 2008-08-27 |
TWI387009B (zh) | 2013-02-21 |
WO2007064472A1 (en) | 2007-06-07 |
DE102005057074B4 (de) | 2009-07-23 |
DE102005057074A1 (de) | 2007-05-31 |
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