FR2847383B1 - Procede de fabrication d'un transistor mos de longueur de grille reduite, et circuit integre comportant un tel transistor - Google Patents

Procede de fabrication d'un transistor mos de longueur de grille reduite, et circuit integre comportant un tel transistor

Info

Publication number
FR2847383B1
FR2847383B1 FR0214255A FR0214255A FR2847383B1 FR 2847383 B1 FR2847383 B1 FR 2847383B1 FR 0214255 A FR0214255 A FR 0214255A FR 0214255 A FR0214255 A FR 0214255A FR 2847383 B1 FR2847383 B1 FR 2847383B1
Authority
FR
France
Prior art keywords
transistor
manufacturing
integrated circuit
substrate
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0214255A
Other languages
English (en)
Other versions
FR2847383A1 (fr
Inventor
Damien Lenoble
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0214255A priority Critical patent/FR2847383B1/fr
Priority to US10/714,440 priority patent/US20040132260A1/en
Publication of FR2847383A1 publication Critical patent/FR2847383A1/fr
Application granted granted Critical
Publication of FR2847383B1 publication Critical patent/FR2847383B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Procédé de fabrication d'un circuit intégré, comprenant un substrat S de silicium cristallin et une grille GR formée sur le substrat S, dans lequel on met en oeuvre une étape d'amorphisation d'une région du substrat S pour obtenir une région de silicium amorphe, on met en oeuvre une étape d'implantation d'une espèce dopante dans une sous-région sensiblement comprise dans ladite région du substrat pour former des extensions de drains et de sources LDD, et on met en oeuvre une étape de formation de source SO et drain DR à basse température.
FR0214255A 2002-11-14 2002-11-14 Procede de fabrication d'un transistor mos de longueur de grille reduite, et circuit integre comportant un tel transistor Expired - Fee Related FR2847383B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0214255A FR2847383B1 (fr) 2002-11-14 2002-11-14 Procede de fabrication d'un transistor mos de longueur de grille reduite, et circuit integre comportant un tel transistor
US10/714,440 US20040132260A1 (en) 2002-11-14 2003-11-14 Process for fabricating a short-gate-length MOS transistor and integrated circuit comprising such a transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0214255A FR2847383B1 (fr) 2002-11-14 2002-11-14 Procede de fabrication d'un transistor mos de longueur de grille reduite, et circuit integre comportant un tel transistor

Publications (2)

Publication Number Publication Date
FR2847383A1 FR2847383A1 (fr) 2004-05-21
FR2847383B1 true FR2847383B1 (fr) 2005-04-15

Family

ID=32187604

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0214255A Expired - Fee Related FR2847383B1 (fr) 2002-11-14 2002-11-14 Procede de fabrication d'un transistor mos de longueur de grille reduite, et circuit integre comportant un tel transistor

Country Status (2)

Country Link
US (1) US20040132260A1 (fr)
FR (1) FR2847383B1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005057074B4 (de) * 2005-11-30 2009-07-23 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Reduzieren von Kristalldefekten in verformten Transistoren durch eine geneigte Voramorphisierung

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2794898B1 (fr) 1999-06-11 2001-09-14 France Telecom Dispositif semi-conducteur a tension de seuil compensee et procede de fabrication
US6989322B2 (en) * 2003-11-25 2006-01-24 International Business Machines Corporation Method of forming ultra-thin silicidation-stop extensions in mosfet devices
WO2006064772A1 (fr) * 2004-12-13 2006-06-22 Matsushita Electric Industrial Co., Ltd. Procede de dopage au plasma
US7531436B2 (en) * 2005-02-14 2009-05-12 Texas Instruments Incorporated Highly conductive shallow junction formation
US7795101B2 (en) * 2006-04-03 2010-09-14 United Microelectronics Corp. Method of forming a MOS transistor
US20080258178A1 (en) * 2006-04-03 2008-10-23 Hsiang-Ying Wang Method of forming a MOS transistor
US7396717B2 (en) * 2006-04-03 2008-07-08 United Microelectronics Corp. Method of forming a MOS transistor
US20070298557A1 (en) * 2006-06-22 2007-12-27 Chun-Feng Nieh Junction leakage reduction in SiGe process by tilt implantation
US7785972B2 (en) * 2006-08-08 2010-08-31 United Microelectronics Corp. Method for fabricating semiconductor MOS device
US7909677B2 (en) * 2007-05-14 2011-03-22 United Microelectronics Corp. Method of transferring a wafer
US7807555B2 (en) * 2007-07-31 2010-10-05 Intersil Americas, Inc. Method of forming the NDMOS device body with the reduced number of masks
CN104779161A (zh) * 2014-01-14 2015-07-15 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4835112A (en) * 1988-03-08 1989-05-30 Motorola, Inc. CMOS salicide process using germanium implantation
US5245208A (en) * 1991-04-22 1993-09-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US6008098A (en) * 1996-10-04 1999-12-28 Advanced Micro Devices, Inc. Ultra shallow junction formation using amorphous silicon layer
US6265293B1 (en) * 1999-08-27 2001-07-24 Advanced Micro Devices, Inc. CMOS transistors fabricated in optimized RTA scheme
US6403433B1 (en) * 1999-09-16 2002-06-11 Advanced Micro Devices, Inc. Source/drain doping technique for ultra-thin-body SOI MOS transistors
US6235599B1 (en) * 1999-10-25 2001-05-22 Advanced Micro Devices, Inc. Fabrication of a shallow doped junction having low sheet resistance using multiple implantations
US6333244B1 (en) * 2000-01-26 2001-12-25 Advanced Micro Devices, Inc. CMOS fabrication process with differential rapid thermal anneal scheme
US6251757B1 (en) * 2000-02-24 2001-06-26 Advanced Micro Devices, Inc. Formation of highly activated shallow abrupt junction by thermal budget engineering
US6297117B1 (en) * 2001-02-12 2001-10-02 Advanced Micro Devices, Inc. Formation of confined halo regions in field effect transistor
JP4845299B2 (ja) * 2001-03-09 2011-12-28 富士通セミコンダクター株式会社 半導体装置の製造方法
US6682980B2 (en) * 2002-05-06 2004-01-27 Texas Instruments Incorporated Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant
DE10260613B8 (de) * 2002-12-23 2010-03-04 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Herstellen eines Feldeffekttransistors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005057074B4 (de) * 2005-11-30 2009-07-23 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Reduzieren von Kristalldefekten in verformten Transistoren durch eine geneigte Voramorphisierung

Also Published As

Publication number Publication date
US20040132260A1 (en) 2004-07-08
FR2847383A1 (fr) 2004-05-21

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Effective date: 20070731