JP2009503889A - 低誘電率膜エッチング後の無損傷アッシングプロセス及びシステム - Google Patents

低誘電率膜エッチング後の無損傷アッシングプロセス及びシステム Download PDF

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Publication number
JP2009503889A
JP2009503889A JP2008524962A JP2008524962A JP2009503889A JP 2009503889 A JP2009503889 A JP 2009503889A JP 2008524962 A JP2008524962 A JP 2008524962A JP 2008524962 A JP2008524962 A JP 2008524962A JP 2009503889 A JP2009503889 A JP 2009503889A
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Japan
Prior art keywords
containing gas
dielectric layer
plasma processing
substrate
plasma
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Pending
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JP2008524962A
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Japanese (ja)
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JP2009503889A5 (https=
Inventor
雅 西野
トリケット，ダグラス，エム
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Publication of JP2009503889A publication Critical patent/JP2009503889A/ja
Publication of JP2009503889A5 publication Critical patent/JP2009503889A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
    • H10P70/234—Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2008524962A 2005-08-03 2006-05-24 低誘電率膜エッチング後の無損傷アッシングプロセス及びシステム Pending JP2009503889A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/195,854 US7279427B2 (en) 2005-08-03 2005-08-03 Damage-free ashing process and system for post low-k etch
PCT/US2006/019914 WO2007018678A2 (en) 2005-08-03 2006-05-24 Damage-free ashing process and system for post low-k etch

Publications (2)

Publication Number Publication Date
JP2009503889A true JP2009503889A (ja) 2009-01-29
JP2009503889A5 JP2009503889A5 (https=) 2009-03-26

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ID=37718178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008524962A Pending JP2009503889A (ja) 2005-08-03 2006-05-24 低誘電率膜エッチング後の無損傷アッシングプロセス及びシステム

Country Status (6)

Country Link
US (1) US7279427B2 (https=)
JP (1) JP2009503889A (https=)
KR (1) KR20080034001A (https=)
CN (1) CN100595891C (https=)
TW (1) TWI336107B (https=)
WO (1) WO2007018678A2 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013528928A (ja) * 2010-03-29 2013-07-11 東京エレクトロン株式会社 低誘電率絶縁体を統合するための方法
JP2015523734A (ja) * 2012-07-10 2015-08-13 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 低ｋ誘電体膜をパターニングする方法
JP2020125223A (ja) * 2019-02-04 2020-08-20 国立大学法人東海国立大学機構 窒化炭素膜の製造方法および窒化炭素被覆体の製造方法

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JP5100057B2 (ja) * 2006-08-18 2012-12-19 東京エレクトロン株式会社 半導体装置の製造方法
US7595005B2 (en) * 2006-12-11 2009-09-29 Tokyo Electron Limited Method and apparatus for ashing a substrate using carbon dioxide
US7637269B1 (en) * 2009-07-29 2009-12-29 Tokyo Electron Limited Low damage method for ashing a substrate using CO2/CO-based process
CN102142393B (zh) * 2010-01-28 2013-07-03 中芯国际集成电路制造(上海)有限公司 互连结构的形成方法
US8916793B2 (en) 2010-06-08 2014-12-23 Applied Materials, Inc. Temperature control in plasma processing apparatus using pulsed heat transfer fluid flow
US9338871B2 (en) 2010-01-29 2016-05-10 Applied Materials, Inc. Feedforward temperature control for plasma processing apparatus
US8741775B2 (en) * 2011-07-20 2014-06-03 Applied Materials, Inc. Method of patterning a low-K dielectric film
US10274270B2 (en) 2011-10-27 2019-04-30 Applied Materials, Inc. Dual zone common catch heat exchanger/chiller
CN103187360B (zh) * 2011-12-30 2016-01-06 中芯国际集成电路制造(上海)有限公司 形成互连结构的方法
US8592327B2 (en) * 2012-03-07 2013-11-26 Tokyo Electron Limited Formation of SiOCl-containing layer on exposed low-k surfaces to reduce low-k damage
CN103545163B (zh) * 2012-07-10 2016-11-16 中芯国际集成电路制造(上海)有限公司 具有氟残留或氯残留的半导体结构的处理方法
US9165783B2 (en) 2012-11-01 2015-10-20 Applied Materials, Inc. Method of patterning a low-k dielectric film
CN103871959B (zh) 2012-12-17 2017-11-03 中芯国际集成电路制造(上海)有限公司 互连结构及其制造方法
CN103871961B (zh) 2012-12-17 2017-08-25 中芯国际集成电路制造(上海)有限公司 互连结构及其制造方法
CN103871962B (zh) 2012-12-18 2017-12-29 中芯国际集成电路制造(上海)有限公司 互连结构及其制造方法
FR3000602B1 (fr) * 2012-12-28 2016-06-24 Commissariat A L Energie Atomique Et Aux Energies Alternatives Procede de gravure d'un materiau dielectrique poreux
US9190317B2 (en) 2013-01-10 2015-11-17 Semiconductor Manufacturing International (Shanghai) Corporation Interconnection structures and fabrication method thereof
US8987139B2 (en) 2013-01-29 2015-03-24 Applied Materials, Inc. Method of patterning a low-k dielectric film
US9385000B2 (en) 2014-01-24 2016-07-05 United Microelectronics Corp. Method of performing etching process
CN103943555B (zh) * 2014-04-28 2016-11-02 上海华力微电子有限公司 一种有源区制备方法
US10312075B2 (en) * 2015-09-30 2019-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Treatment system and method
US10199223B2 (en) * 2016-01-26 2019-02-05 Asm Ip Holding B.V. Semiconductor device fabrication using etch stop layer
CN109742019B (zh) * 2019-01-21 2019-10-01 广东工业大学 一种利用紫外激光加工干法刻蚀中硬掩膜板的方法
US20230268223A1 (en) * 2022-02-24 2023-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture

Citations (3)

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JP2001077086A (ja) * 1999-08-31 2001-03-23 Oki Electric Ind Co Ltd 半導体装置のドライエッチング方法
WO2003090267A1 (en) * 2002-04-16 2003-10-30 Tokyo Electron Limited Method for removing photoresist and etch residues
JP2004158691A (ja) * 2002-11-07 2004-06-03 Yac Co Ltd レジスト除去方法

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JP3193265B2 (ja) * 1995-05-20 2001-07-30 東京エレクトロン株式会社 プラズマエッチング装置
US6967173B2 (en) * 2000-11-15 2005-11-22 Texas Instruments Incorporated Hydrogen plasma photoresist strip and polymeric residue cleanup processs for low dielectric constant materials
CN1226455C (zh) * 2002-07-19 2005-11-09 联华电子股份有限公司 预清除用氟化碳反应气体的蚀刻工艺后残留聚合物的方法
US7833957B2 (en) * 2002-08-22 2010-11-16 Daikin Industries, Ltd. Removing solution
US7344991B2 (en) * 2002-12-23 2008-03-18 Tokyo Electron Limited Method and apparatus for multilayer photoresist dry development
WO2004061919A1 (en) * 2002-12-23 2004-07-22 Tokyo Electron Limited Method and apparatus for bilayer photoresist dry development
US7309448B2 (en) * 2003-08-08 2007-12-18 Applied Materials, Inc. Selective etch process of a sacrificial light absorbing material (SLAM) over a dielectric material
US7176141B2 (en) * 2004-09-07 2007-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Plasma treatment to improve barrier layer performance over porous low-K insulating dielectrics

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077086A (ja) * 1999-08-31 2001-03-23 Oki Electric Ind Co Ltd 半導体装置のドライエッチング方法
WO2003090267A1 (en) * 2002-04-16 2003-10-30 Tokyo Electron Limited Method for removing photoresist and etch residues
JP2005523585A (ja) * 2002-04-16 2005-08-04 東京エレクトロン株式会社 フォトレジストおよびエッチング残渣の除去方法
JP2004158691A (ja) * 2002-11-07 2004-06-03 Yac Co Ltd レジスト除去方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013528928A (ja) * 2010-03-29 2013-07-11 東京エレクトロン株式会社 低誘電率絶縁体を統合するための方法
JP2015523734A (ja) * 2012-07-10 2015-08-13 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 低ｋ誘電体膜をパターニングする方法
JP2020125223A (ja) * 2019-02-04 2020-08-20 国立大学法人東海国立大学機構 窒化炭素膜の製造方法および窒化炭素被覆体の製造方法
JP7296093B2 (ja) 2019-02-04 2023-06-22 国立大学法人東海国立大学機構 窒化炭素膜の製造方法および窒化炭素被覆体の製造方法

Also Published As

Publication number Publication date
WO2007018678A2 (en) 2007-02-15
TW200721300A (en) 2007-06-01
CN100595891C (zh) 2010-03-24
WO2007018678A3 (en) 2007-07-12
CN101238551A (zh) 2008-08-06
US7279427B2 (en) 2007-10-09
US20070032087A1 (en) 2007-02-08
KR20080034001A (ko) 2008-04-17
TWI336107B (en) 2011-01-11

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