JP2015523734A - 低k誘電体膜をパターニングする方法 - Google Patents
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- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
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- H01J37/32—Gas-filled discharge tubes
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- H01J37/32357—Generation remote from the workpiece, e.g. down-stream
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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Abstract
Description
本発明の実施形態は、半導体処理の分野に関し、特に、低k誘電体膜をパターニングする方法に関する。
半導体製造では、低k誘電体は、二酸化ケイ素に対して小さい誘電率を有する材料である。低k誘電体材料の実装は、マイクロ電子デバイスの継続的なスケーリングを可能にするために使用されるいくつかの戦略のうちの一つである。デジタル回路では、絶縁性誘電体は、導電性部品(例えば、ワイヤ相互接続及びトランジスタ)を互いに分離する。部品がスケーリングされ、トランジスタが共により接近するにつれて、絶縁性誘電体は、電荷の蓄積及びクロストークがデバイスの性能に悪影響を及ぼす点まで薄くなってきている。同じ厚さの低k誘電体で二酸化ケイ素を置き換えることは、寄生容量を減少させ、より速いスイッチング速度とより低い熱放散を可能にする。
Claims (15)
- 低k誘電体膜をパターニングする方法であって、
基板の上方に配置された低k誘電体層の上方にマスク層を形成してパターニングする工程と、
プラズマプロセスで低k誘電体層の露出部分を改質する工程と、
同一操作内で、リモートプラズマプロセスによって、低k誘電体層の改質された部分を、マスク層及び低k誘電体層の非改質部分に対して選択的に除去する工程を含む方法。 - プラズマプロセスで低k誘電体層の露出部分を改質する工程は、SiF4/N2/Arベースのプラズマを用いる工程を含む請求項1記載の方法。
- Arは、約5〜50ミリトールの範囲内の圧力を有し、プラズマは、約10〜1000Wの範囲内の出力を有する請求項2記載の方法。
- リモートプラズマプロセスによって、低k誘電体層の改質された部分を除去する工程は、NF3/O2/N2、CF4/O2/N2、及びNF3/NH3プラズマのリモートプラズマからなる群から選択されるプラズマを使用する工程を含む請求項1記載の方法。
- プラズマプロセスで低k誘電体層の露出部分を改質する工程は、プラズマプロセスによって、マスク層上に保護材料層を形成する工程を含む請求項1記載の方法。
- マスク層を形成してパターニングする工程は、窒化チタン及び窒カタン樽からなる軍から選択される材料を形成しパターニングする工程を含む請求項1記載の方法。
- マスク層を形成してパターニングする工程は、非酸化物誘電体材料を形成しパターニングする工程を含む請求項1記載の方法。
- マスク層を形成してパターニングする工程は、フォトレジスト層を形成しパターニングする工程を含む請求項1記載の方法。
- 低k誘電体層の上方にマスク層を形成してパターニングする工程は、フッ素ドープ二酸化ケイ素、炭素ドープ二酸化ケイ素、多孔質二酸化ケイ素、多孔質炭素ドープ二酸化ケイ素、多孔質SiLK、スピンオンシリコーンベースのポリマー誘電体、スピンオン有機ポリマー誘電体、及び2.7未満の誘電率を有する多孔質SiCOH層からなる群から選択される低k誘電体材料の上方にマスク層を形成してパターニングする工程を含む請求項1記載の方法。
- 低k誘電体膜をパターニングする方法であって、
基板の上方に配置された低k誘電体層の上方にマスク層を形成してパターニングする工程と、
チャンバ内においてSiF4/N2/Arベースのプラズマプロセスで低k誘電体層の露出部分を改質する工程と、
同一チャンバ内で、NF3/O2/N2、CF4/O2/N2、及びNF3/NH3プラズマのリモートプラズマからなる群から選択されるプラズマに基づくリモートプラズマプロセスによって、低k誘電体層の改質された部分を、マスク層及び低k誘電体層の非改質部分に対して選択的に除去する工程を含む方法。 - SiF4/N2/ArベースのプラズマプロセスのArは、約5〜50ミリトールの範囲内の圧力を有し、プラズマは、約10〜1000Wの範囲内の出力を有する請求項10記載の方法。
- プラズマプロセスで低k誘電体層の露出部分を改質する工程は、プラズマプロセスによって、マスク層上に保護材料層を形成する工程を含む請求項10記載の方法。
- マスク層を形成してパターニングする工程は、窒化チタン及び窒化タンタルからなる群から選択される材料を形成しパターニングする工程を含む請求項10記載の方法。
- マスク層を形成してパターニングする工程は、非酸化物誘電体材料を形成しパターニングする工程を含む請求項10記載の方法。
- マスク層を形成してパターニングする工程は、フォトレジスト層を形成しパターニングする工程を含む請求項10記載の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201261669824P | 2012-07-10 | 2012-07-10 | |
US61/669,824 | 2012-07-10 | ||
US13/922,543 | 2013-06-20 | ||
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PCT/US2013/047164 WO2014011382A1 (en) | 2012-07-10 | 2013-06-21 | Method of patterning a low-k dielectric film |
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TW201407685A (zh) | 2014-02-16 |
JP6457937B2 (ja) | 2019-01-23 |
KR102033685B1 (ko) | 2019-10-17 |
WO2014011382A1 (en) | 2014-01-16 |
US20140017898A1 (en) | 2014-01-16 |
TWI591725B (zh) | 2017-07-11 |
US8802572B2 (en) | 2014-08-12 |
KR20150036534A (ko) | 2015-04-07 |
CN104395990A (zh) | 2015-03-04 |
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